\doxysection{stm32h7xx\+\_\+ll\+\_\+rcc.\+h}
\hypertarget{stm32h7xx__ll__rcc_8h_source}{}\label{stm32h7xx__ll__rcc_8h_source}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_ll\_rcc.h@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_ll\_rcc.h}}
\mbox{\hyperlink{stm32h7xx__ll__rcc_8h}{Go to the documentation of this file.}}
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\DoxyCodeLine{00450\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_4\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_2)}}
\DoxyCodeLine{00451\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_5\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00452\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_6\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_1)}}
\DoxyCodeLine{00453\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_7\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_1|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00454\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_8\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_3)}}
\DoxyCodeLine{00455\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_9\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00456\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_10\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_1)}}
\DoxyCodeLine{00457\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_11\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_1|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00458\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_12\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_2)}}
\DoxyCodeLine{00459\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_13\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00460\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_14\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_1)}}
\DoxyCodeLine{00461\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_15\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_1|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00462\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_16\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_4)}}
\DoxyCodeLine{00463\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_17\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00464\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_18\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_1)}}
\DoxyCodeLine{00465\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_19\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_1|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00466\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_20\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_2)}}
\DoxyCodeLine{00467\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_21\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00468\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_22\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_1)}}
\DoxyCodeLine{00469\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_23\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_1|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00470\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_24\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_3)}}
\DoxyCodeLine{00471\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_25\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00472\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_26\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_1)}}
\DoxyCodeLine{00473\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_27\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_1|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00474\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_28\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_2)}}
\DoxyCodeLine{00475\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_29\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00476\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_30\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_1)}}
\DoxyCodeLine{00477\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_31\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_1|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00478\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_32\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5)}}
\DoxyCodeLine{00479\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_33\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00480\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_34\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_1)}}
\DoxyCodeLine{00481\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_35\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_1|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00482\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_36\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_2)}}
\DoxyCodeLine{00483\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_37\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00484\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_38\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_1)}}
\DoxyCodeLine{00485\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_39\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_1|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00486\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_40\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_3)}}
\DoxyCodeLine{00487\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_41\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00488\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_42\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_1)}}
\DoxyCodeLine{00489\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_43\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_1|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00490\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_44\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_2)}}
\DoxyCodeLine{00491\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_45\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00492\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_46\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_1)}}
\DoxyCodeLine{00493\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_47\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_1|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00494\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_48\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_4)}}
\DoxyCodeLine{00495\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_49\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00496\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_50\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_1)}}
\DoxyCodeLine{00497\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_51\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_1|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00498\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_52\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_2)}}
\DoxyCodeLine{00499\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_53\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00500\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_54\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_1)}}
\DoxyCodeLine{00501\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_55\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_1|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00502\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_56\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_3)}}
\DoxyCodeLine{00503\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_57\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00504\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_58\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_1)}}
\DoxyCodeLine{00505\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_59\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_1|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00506\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_60\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_2)}}
\DoxyCodeLine{00507\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_61\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_0)}}
\DoxyCodeLine{00508\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_62\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_1)}}
\DoxyCodeLine{00509\ \textcolor{preprocessor}{\#define\ LL\_RCC\_RTC\_HSE\_DIV\_63\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (uint32\_t)(RCC\_CFGR\_RTCPRE\_5|RCC\_CFGR\_RTCPRE\_4|RCC\_CFGR\_RTCPRE\_3|RCC\_CFGR\_RTCPRE\_2|RCC\_CFGR\_RTCPRE\_1|RCC\_CFGR\_RTCPRE\_0)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00513\ }
\DoxyCodeLine{00517\ \textcolor{preprocessor}{\#if\ defined(RCC\_D2CCIP2R\_USART16SEL)}}
\DoxyCodeLine{00518\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16\_CLKSOURCE\_PCLK2\ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_USART16SEL,\ RCC\_D2CCIP2R\_USART16SEL\_Pos,\ 0x00000000U)}}
\DoxyCodeLine{00519\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16\_CLKSOURCE\_PLL2Q\ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_USART16SEL,\ RCC\_D2CCIP2R\_USART16SEL\_Pos,\ RCC\_D2CCIP2R\_USART16SEL\_0)}}
\DoxyCodeLine{00520\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16\_CLKSOURCE\_PLL3Q\ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_USART16SEL,\ RCC\_D2CCIP2R\_USART16SEL\_Pos,\ RCC\_D2CCIP2R\_USART16SEL\_1)}}
\DoxyCodeLine{00521\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16\_CLKSOURCE\_HSI\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_USART16SEL,\ RCC\_D2CCIP2R\_USART16SEL\_Pos,\ RCC\_D2CCIP2R\_USART16SEL\_0\ |\ RCC\_D2CCIP2R\_USART16SEL\_1)}}
\DoxyCodeLine{00522\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16\_CLKSOURCE\_CSI\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_USART16SEL,\ RCC\_D2CCIP2R\_USART16SEL\_Pos,\ RCC\_D2CCIP2R\_USART16SEL\_2)}}
\DoxyCodeLine{00523\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16\_CLKSOURCE\_LSE\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_USART16SEL,\ RCC\_D2CCIP2R\_USART16SEL\_Pos,\ RCC\_D2CCIP2R\_USART16SEL\_0\ |\ RCC\_D2CCIP2R\_USART16SEL\_2)}}
\DoxyCodeLine{00524\ \textcolor{comment}{/*\ \ Aliases\ */}}
\DoxyCodeLine{00525\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16910\_CLKSOURCE\_PCLK2\ \ \ \ \ \ LL\_RCC\_USART16\_CLKSOURCE\_PCLK2}}
\DoxyCodeLine{00526\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16910\_CLKSOURCE\_PLL2Q\ \ \ \ \ \ LL\_RCC\_USART16\_CLKSOURCE\_PLL2Q}}
\DoxyCodeLine{00527\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16910\_CLKSOURCE\_PLL3Q\ \ \ \ \ \ LL\_RCC\_USART16\_CLKSOURCE\_PLL3Q}}
\DoxyCodeLine{00528\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16910\_CLKSOURCE\_HSI\ \ \ \ \ \ \ \ LL\_RCC\_USART16\_CLKSOURCE\_HSI}}
\DoxyCodeLine{00529\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16910\_CLKSOURCE\_CSI\ \ \ \ \ \ \ \ LL\_RCC\_USART16\_CLKSOURCE\_CSI}}
\DoxyCodeLine{00530\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16910\_CLKSOURCE\_LSE\ \ \ \ \ \ \ \ LL\_RCC\_USART16\_CLKSOURCE\_LSE}}
\DoxyCodeLine{00531\ }
\DoxyCodeLine{00532\ \textcolor{preprocessor}{\#elif\ defined(RCC\_D2CCIP2R\_USART16910SEL)}}
\DoxyCodeLine{00533\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16910\_CLKSOURCE\_PCLK2\ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_USART16910SEL,\ RCC\_D2CCIP2R\_USART16910SEL\_Pos,\ 0x00000000U)}}
\DoxyCodeLine{00534\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16910\_CLKSOURCE\_PLL2Q\ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_USART16910SEL,\ RCC\_D2CCIP2R\_USART16910SEL\_Pos,\ RCC\_D2CCIP2R\_USART16910SEL\_0)}}
\DoxyCodeLine{00535\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16910\_CLKSOURCE\_PLL3Q\ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_USART16910SEL,\ RCC\_D2CCIP2R\_USART16910SEL\_Pos,\ RCC\_D2CCIP2R\_USART16910SEL\_1)}}
\DoxyCodeLine{00536\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16910\_CLKSOURCE\_HSI\ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_USART16910SEL,\ RCC\_D2CCIP2R\_USART16910SEL\_Pos,\ RCC\_D2CCIP2R\_USART16910SEL\_0\ |\ RCC\_D2CCIP2R\_USART16910SEL\_1)}}
\DoxyCodeLine{00537\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16910\_CLKSOURCE\_CSI\ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_USART16910SEL,\ RCC\_D2CCIP2R\_USART16910SEL\_Pos,\ RCC\_D2CCIP2R\_USART16910SEL\_2)}}
\DoxyCodeLine{00538\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16910\_CLKSOURCE\_LSE\ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_USART16910SEL,\ RCC\_D2CCIP2R\_USART16910SEL\_Pos,\ RCC\_D2CCIP2R\_USART16910SEL\_0\ |\ RCC\_D2CCIP2R\_USART16910SEL\_2)}}
\DoxyCodeLine{00539\ \textcolor{comment}{/*\ \ Aliases\ */}}
\DoxyCodeLine{00540\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16\_CLKSOURCE\_PCLK2\ \ \ \ \ \ \ \ \ LL\_RCC\_USART16910\_CLKSOURCE\_PCLK2}}
\DoxyCodeLine{00541\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16\_CLKSOURCE\_PLL2Q\ \ \ \ \ \ \ \ \ LL\_RCC\_USART16910\_CLKSOURCE\_PLL2Q}}
\DoxyCodeLine{00542\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16\_CLKSOURCE\_PLL3Q\ \ \ \ \ \ \ \ \ LL\_RCC\_USART16910\_CLKSOURCE\_PLL3Q}}
\DoxyCodeLine{00543\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16\_CLKSOURCE\_HSI\ \ \ \ \ \ \ \ \ \ \ LL\_RCC\_USART16910\_CLKSOURCE\_HSI}}
\DoxyCodeLine{00544\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16\_CLKSOURCE\_CSI\ \ \ \ \ \ \ \ \ \ \ LL\_RCC\_USART16910\_CLKSOURCE\_CSI}}
\DoxyCodeLine{00545\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16\_CLKSOURCE\_LSE\ \ \ \ \ \ \ \ \ \ \ LL\_RCC\_USART16910\_CLKSOURCE\_LSE}}
\DoxyCodeLine{00546\ }
\DoxyCodeLine{00547\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{00548\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16910\_CLKSOURCE\_PCLK2\ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP2,\ RCC\_CDCCIP2R\_USART16910SEL,\ RCC\_CDCCIP2R\_USART16910SEL\_Pos,\ 0x00000000U)}}
\DoxyCodeLine{00549\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16910\_CLKSOURCE\_PLL2Q\ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP2,\ RCC\_CDCCIP2R\_USART16910SEL,\ RCC\_CDCCIP2R\_USART16910SEL\_Pos,\ RCC\_CDCCIP2R\_USART16910SEL\_0)}}
\DoxyCodeLine{00550\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16910\_CLKSOURCE\_PLL3Q\ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP2,\ RCC\_CDCCIP2R\_USART16910SEL,\ RCC\_CDCCIP2R\_USART16910SEL\_Pos,\ RCC\_CDCCIP2R\_USART16910SEL\_1)}}
\DoxyCodeLine{00551\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16910\_CLKSOURCE\_HSI\ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP2,\ RCC\_CDCCIP2R\_USART16910SEL,\ RCC\_CDCCIP2R\_USART16910SEL\_Pos,\ RCC\_CDCCIP2R\_USART16910SEL\_0\ |\ RCC\_CDCCIP2R\_USART16910SEL\_1)}}
\DoxyCodeLine{00552\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16910\_CLKSOURCE\_CSI\ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP2,\ RCC\_CDCCIP2R\_USART16910SEL,\ RCC\_CDCCIP2R\_USART16910SEL\_Pos,\ RCC\_CDCCIP2R\_USART16910SEL\_2)}}
\DoxyCodeLine{00553\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16910\_CLKSOURCE\_LSE\ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP2,\ RCC\_CDCCIP2R\_USART16910SEL,\ RCC\_CDCCIP2R\_USART16910SEL\_Pos,\ RCC\_CDCCIP2R\_USART16910SEL\_0\ |\ RCC\_CDCCIP2R\_USART16910SEL\_2)}}
\DoxyCodeLine{00554\ \textcolor{comment}{/*\ \ Aliases\ */}}
\DoxyCodeLine{00555\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16\_CLKSOURCE\_PCLK2\ \ \ \ \ \ \ \ \ LL\_RCC\_USART16910\_CLKSOURCE\_PCLK2}}
\DoxyCodeLine{00556\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16\_CLKSOURCE\_PLL2Q\ \ \ \ \ \ \ \ \ LL\_RCC\_USART16910\_CLKSOURCE\_PLL2Q}}
\DoxyCodeLine{00557\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16\_CLKSOURCE\_PLL3Q\ \ \ \ \ \ \ \ \ LL\_RCC\_USART16910\_CLKSOURCE\_PLL3Q}}
\DoxyCodeLine{00558\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16\_CLKSOURCE\_HSI\ \ \ \ \ \ \ \ \ \ \ LL\_RCC\_USART16910\_CLKSOURCE\_HSI}}
\DoxyCodeLine{00559\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16\_CLKSOURCE\_CSI\ \ \ \ \ \ \ \ \ \ \ LL\_RCC\_USART16910\_CLKSOURCE\_CSI}}
\DoxyCodeLine{00560\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART16\_CLKSOURCE\_LSE\ \ \ \ \ \ \ \ \ \ \ LL\_RCC\_USART16910\_CLKSOURCE\_LSE}}
\DoxyCodeLine{00561\ \textcolor{preprocessor}{\#endif\ \ }\textcolor{comment}{/*\ RCC\_D2CCIP2R\_USART16SEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00562\ \textcolor{preprocessor}{\#if\ defined(RCC\_D2CCIP2R\_USART28SEL)}}
\DoxyCodeLine{00563\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART234578\_CLKSOURCE\_PCLK1\ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_USART28SEL,\ RCC\_D2CCIP2R\_USART28SEL\_Pos,\ 0x00000000U)}}
\DoxyCodeLine{00564\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART234578\_CLKSOURCE\_PLL2Q\ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_USART28SEL,\ RCC\_D2CCIP2R\_USART28SEL\_Pos,\ RCC\_D2CCIP2R\_USART28SEL\_0)}}
\DoxyCodeLine{00565\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART234578\_CLKSOURCE\_PLL3Q\ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_USART28SEL,\ RCC\_D2CCIP2R\_USART28SEL\_Pos,\ RCC\_D2CCIP2R\_USART28SEL\_1)}}
\DoxyCodeLine{00566\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART234578\_CLKSOURCE\_HSI\ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_USART28SEL,\ RCC\_D2CCIP2R\_USART28SEL\_Pos,\ RCC\_D2CCIP2R\_USART28SEL\_0\ |\ RCC\_D2CCIP2R\_USART28SEL\_1)}}
\DoxyCodeLine{00567\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART234578\_CLKSOURCE\_CSI\ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_USART28SEL,\ RCC\_D2CCIP2R\_USART28SEL\_Pos,\ RCC\_D2CCIP2R\_USART28SEL\_2)}}
\DoxyCodeLine{00568\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART234578\_CLKSOURCE\_LSE\ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_USART28SEL,\ RCC\_D2CCIP2R\_USART28SEL\_Pos,\ RCC\_D2CCIP2R\_USART28SEL\_0\ |\ RCC\_D2CCIP2R\_USART28SEL\_2)}}
\DoxyCodeLine{00569\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{00570\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART234578\_CLKSOURCE\_PCLK1\ \ \ \ \ LL\_CLKSOURCE(CDCCIP2,\ RCC\_CDCCIP2R\_USART234578SEL,\ RCC\_CDCCIP2R\_USART234578SEL\_Pos,\ 0x00000000U)}}
\DoxyCodeLine{00571\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART234578\_CLKSOURCE\_PLL2Q\ \ \ \ \ LL\_CLKSOURCE(CDCCIP2,\ RCC\_CDCCIP2R\_USART234578SEL,\ RCC\_CDCCIP2R\_USART234578SEL\_Pos,\ RCC\_CDCCIP2R\_USART234578SEL\_0)}}
\DoxyCodeLine{00572\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART234578\_CLKSOURCE\_PLL3Q\ \ \ \ \ LL\_CLKSOURCE(CDCCIP2,\ RCC\_CDCCIP2R\_USART234578SEL,\ RCC\_CDCCIP2R\_USART234578SEL\_Pos,\ RCC\_CDCCIP2R\_USART234578SEL\_1)}}
\DoxyCodeLine{00573\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART234578\_CLKSOURCE\_HSI\ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP2,\ RCC\_CDCCIP2R\_USART234578SEL,\ RCC\_CDCCIP2R\_USART234578SEL\_Pos,\ RCC\_CDCCIP2R\_USART234578SEL\_0\ |\ RCC\_CDCCIP2R\_USART234578SEL\_1)}}
\DoxyCodeLine{00574\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART234578\_CLKSOURCE\_CSI\ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP2,\ RCC\_CDCCIP2R\_USART234578SEL,\ RCC\_CDCCIP2R\_USART234578SEL\_Pos,\ RCC\_CDCCIP2R\_USART234578SEL\_2)}}
\DoxyCodeLine{00575\ \textcolor{preprocessor}{\#define\ LL\_RCC\_USART234578\_CLKSOURCE\_LSE\ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP2,\ RCC\_CDCCIP2R\_USART234578SEL,\ RCC\_CDCCIP2R\_USART234578SEL\_Pos,\ RCC\_CDCCIP2R\_USART234578SEL\_0\ |\ RCC\_CDCCIP2R\_USART234578SEL\_2)}}
\DoxyCodeLine{00576\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D2CCIP2R\_USART28SEL\ */}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{00580\ }
\DoxyCodeLine{00584\ \textcolor{preprocessor}{\#if\ defined(RCC\_D3CCIPR\_LPUART1SEL)}}
\DoxyCodeLine{00585\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPUART1\_CLKSOURCE\_PCLK4\ \ \ \ \ \ \ \ \ (0x00000000U)}}
\DoxyCodeLine{00586\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPUART1\_CLKSOURCE\_PLL2Q\ \ \ \ \ \ \ \ \ (RCC\_D3CCIPR\_LPUART1SEL\_0)}}
\DoxyCodeLine{00587\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPUART1\_CLKSOURCE\_PLL3Q\ \ \ \ \ \ \ \ \ (RCC\_D3CCIPR\_LPUART1SEL\_1)}}
\DoxyCodeLine{00588\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPUART1\_CLKSOURCE\_HSI\ \ \ \ \ \ \ \ \ \ \ (RCC\_D3CCIPR\_LPUART1SEL\_0\ |\ RCC\_D3CCIPR\_LPUART1SEL\_1)}}
\DoxyCodeLine{00589\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPUART1\_CLKSOURCE\_CSI\ \ \ \ \ \ \ \ \ \ \ (RCC\_D3CCIPR\_LPUART1SEL\_2)}}
\DoxyCodeLine{00590\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPUART1\_CLKSOURCE\_LSE\ \ \ \ \ \ \ \ \ \ \ (RCC\_D3CCIPR\_LPUART1SEL\_0\ |\ RCC\_D3CCIPR\_LPUART1SEL\_2)}}
\DoxyCodeLine{00591\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{00592\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPUART1\_CLKSOURCE\_PCLK4\ \ \ \ \ \ \ \ \ (0x00000000U)}}
\DoxyCodeLine{00593\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPUART1\_CLKSOURCE\_PLL2Q\ \ \ \ \ \ \ \ \ (RCC\_SRDCCIPR\_LPUART1SEL\_0)}}
\DoxyCodeLine{00594\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPUART1\_CLKSOURCE\_PLL3Q\ \ \ \ \ \ \ \ \ (RCC\_SRDCCIPR\_LPUART1SEL\_1)}}
\DoxyCodeLine{00595\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPUART1\_CLKSOURCE\_HSI\ \ \ \ \ \ \ \ \ \ \ (RCC\_SRDCCIPR\_LPUART1SEL\_0\ |\ RCC\_SRDCCIPR\_LPUART1SEL\_1)}}
\DoxyCodeLine{00596\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPUART1\_CLKSOURCE\_CSI\ \ \ \ \ \ \ \ \ \ \ (RCC\_SRDCCIPR\_LPUART1SEL\_2)}}
\DoxyCodeLine{00597\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPUART1\_CLKSOURCE\_LSE\ \ \ \ \ \ \ \ \ \ \ (RCC\_SRDCCIPR\_LPUART1SEL\_0\ |\ RCC\_SRDCCIPR\_LPUART1SEL\_2)}}
\DoxyCodeLine{00598\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D3CCIPR\_LPUART1SEL\ */}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{00602\ }
\DoxyCodeLine{00606\ \textcolor{preprocessor}{\#if\ defined\ (RCC\_D2CCIP2R\_I2C123SEL)}}
\DoxyCodeLine{00607\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C123\_CLKSOURCE\_PCLK1\ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_I2C123SEL,\ RCC\_D2CCIP2R\_I2C123SEL\_Pos,\ 0x00000000U)}}
\DoxyCodeLine{00608\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C123\_CLKSOURCE\_PLL3R\ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_I2C123SEL,\ RCC\_D2CCIP2R\_I2C123SEL\_Pos,\ RCC\_D2CCIP2R\_I2C123SEL\_0)}}
\DoxyCodeLine{00609\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C123\_CLKSOURCE\_HSI\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_I2C123SEL,\ RCC\_D2CCIP2R\_I2C123SEL\_Pos,\ RCC\_D2CCIP2R\_I2C123SEL\_1)}}
\DoxyCodeLine{00610\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C123\_CLKSOURCE\_CSI\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_I2C123SEL,\ RCC\_D2CCIP2R\_I2C123SEL\_Pos,\ RCC\_D2CCIP2R\_I2C123SEL\_0\ |\ RCC\_D2CCIP2R\_I2C123SEL\_1)}}
\DoxyCodeLine{00611\ \textcolor{comment}{/*\ \ Aliases\ */}}
\DoxyCodeLine{00612\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C1235\_CLKSOURCE\_PCLK1\ \ \ \ \ \ \ \ \ LL\_RCC\_I2C123\_CLKSOURCE\_PCLK1}}
\DoxyCodeLine{00613\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C1235\_CLKSOURCE\_PLL3R\ \ \ \ \ \ \ \ \ LL\_RCC\_I2C123\_CLKSOURCE\_PLL3R}}
\DoxyCodeLine{00614\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C1235\_CLKSOURCE\_HSI\ \ \ \ \ \ \ \ \ \ \ LL\_RCC\_I2C123\_CLKSOURCE\_HSI}}
\DoxyCodeLine{00615\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C1235\_CLKSOURCE\_CSI\ \ \ \ \ \ \ \ \ \ \ LL\_RCC\_I2C123\_CLKSOURCE\_CSI}}
\DoxyCodeLine{00616\ }
\DoxyCodeLine{00617\ \textcolor{preprocessor}{\#elif\ defined\ (RCC\_D2CCIP2R\_I2C1235SEL)}}
\DoxyCodeLine{00618\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C1235\_CLKSOURCE\_PCLK1\ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_I2C1235SEL,\ RCC\_D2CCIP2R\_I2C1235SEL\_Pos,\ 0x00000000U)}}
\DoxyCodeLine{00619\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C1235\_CLKSOURCE\_PLL3R\ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_I2C1235SEL,\ RCC\_D2CCIP2R\_I2C1235SEL\_Pos,\ RCC\_D2CCIP2R\_I2C1235SEL\_0)}}
\DoxyCodeLine{00620\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C1235\_CLKSOURCE\_HSI\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_I2C1235SEL,\ RCC\_D2CCIP2R\_I2C1235SEL\_Pos,\ RCC\_D2CCIP2R\_I2C1235SEL\_1)}}
\DoxyCodeLine{00621\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C1235\_CLKSOURCE\_CSI\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_I2C1235SEL,\ RCC\_D2CCIP2R\_I2C1235SEL\_Pos,\ RCC\_D2CCIP2R\_I2C1235SEL\_0\ |\ RCC\_D2CCIP2R\_I2C1235SEL\_1)}}
\DoxyCodeLine{00622\ \textcolor{comment}{/*\ \ Aliases\ */}}
\DoxyCodeLine{00623\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C123\_CLKSOURCE\_PCLK1\ \ \ \ \ \ \ \ \ \ LL\_RCC\_I2C1235\_CLKSOURCE\_PCLK1}}
\DoxyCodeLine{00624\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C123\_CLKSOURCE\_PLL3R\ \ \ \ \ \ \ \ \ \ LL\_RCC\_I2C1235\_CLKSOURCE\_PLL3R}}
\DoxyCodeLine{00625\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C123\_CLKSOURCE\_HSI\ \ \ \ \ \ \ \ \ \ \ \ LL\_RCC\_I2C1235\_CLKSOURCE\_HSI}}
\DoxyCodeLine{00626\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C123\_CLKSOURCE\_CSI\ \ \ \ \ \ \ \ \ \ \ \ LL\_RCC\_I2C1235\_CLKSOURCE\_CSI}}
\DoxyCodeLine{00627\ }
\DoxyCodeLine{00628\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{00629\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C123\_CLKSOURCE\_PCLK1\ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP2,\ RCC\_CDCCIP2R\_I2C123SEL,\ RCC\_CDCCIP2R\_I2C123SEL\_Pos,\ 0x00000000U)}}
\DoxyCodeLine{00630\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C123\_CLKSOURCE\_PLL3R\ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP2,\ RCC\_CDCCIP2R\_I2C123SEL,\ RCC\_CDCCIP2R\_I2C123SEL\_Pos,\ RCC\_CDCCIP2R\_I2C123SEL\_0)}}
\DoxyCodeLine{00631\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C123\_CLKSOURCE\_HSI\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP2,\ RCC\_CDCCIP2R\_I2C123SEL,\ RCC\_CDCCIP2R\_I2C123SEL\_Pos,\ RCC\_CDCCIP2R\_I2C123SEL\_1)}}
\DoxyCodeLine{00632\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C123\_CLKSOURCE\_CSI\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP2,\ RCC\_CDCCIP2R\_I2C123SEL,\ RCC\_CDCCIP2R\_I2C123SEL\_Pos,\ RCC\_CDCCIP2R\_I2C123SEL\_0\ |\ RCC\_CDCCIP2R\_I2C123SEL\_1)}}
\DoxyCodeLine{00633\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D2CCIP2R\_I2C123SEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00634\ \textcolor{preprocessor}{\#if\ defined\ (RCC\_D3CCIPR\_I2C4SEL)}}
\DoxyCodeLine{00635\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C4\_CLKSOURCE\_PCLK4\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_I2C4SEL,\ \ \ \ RCC\_D3CCIPR\_I2C4SEL\_Pos,\ \ \ \ 0x00000000U)}}
\DoxyCodeLine{00636\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C4\_CLKSOURCE\_PLL3R\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_I2C4SEL,\ \ \ \ RCC\_D3CCIPR\_I2C4SEL\_Pos,\ \ \ \ RCC\_D3CCIPR\_I2C4SEL\_0)}}
\DoxyCodeLine{00637\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C4\_CLKSOURCE\_HSI\ \ \ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_I2C4SEL,\ \ \ \ RCC\_D3CCIPR\_I2C4SEL\_Pos,\ \ \ \ RCC\_D3CCIPR\_I2C4SEL\_1)}}
\DoxyCodeLine{00638\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C4\_CLKSOURCE\_CSI\ \ \ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_I2C4SEL,\ \ \ \ RCC\_D3CCIPR\_I2C4SEL\_Pos,\ \ \ \ RCC\_D3CCIPR\_I2C4SEL\_0\ |\ RCC\_D3CCIPR\_I2C4SEL\_1)}}
\DoxyCodeLine{00639\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{00640\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C4\_CLKSOURCE\_PCLK4\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(SRDCCIP,\ \ RCC\_SRDCCIPR\_I2C4SEL,\ \ \ \ RCC\_SRDCCIPR\_I2C4SEL\_Pos,\ \ \ \ 0x00000000U)}}
\DoxyCodeLine{00641\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C4\_CLKSOURCE\_PLL3R\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(SRDCCIP,\ \ RCC\_SRDCCIPR\_I2C4SEL,\ \ \ \ RCC\_SRDCCIPR\_I2C4SEL\_Pos,\ \ \ \ RCC\_SRDCCIPR\_I2C4SEL\_0)}}
\DoxyCodeLine{00642\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C4\_CLKSOURCE\_HSI\ \ \ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(SRDCCIP,\ \ RCC\_SRDCCIPR\_I2C4SEL,\ \ \ \ RCC\_SRDCCIPR\_I2C4SEL\_Pos,\ \ \ \ RCC\_SRDCCIPR\_I2C4SEL\_1)}}
\DoxyCodeLine{00643\ \textcolor{preprocessor}{\#define\ LL\_RCC\_I2C4\_CLKSOURCE\_CSI\ \ \ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(SRDCCIP,\ \ RCC\_SRDCCIPR\_I2C4SEL,\ \ \ \ RCC\_SRDCCIPR\_I2C4SEL\_Pos,\ \ \ \ RCC\_SRDCCIPR\_I2C4SEL\_0\ |\ RCC\_SRDCCIPR\_I2C4SEL\_1)}}
\DoxyCodeLine{00644\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D3CCIPR\_I2C4SEL\ */}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{00648\ }
\DoxyCodeLine{00652\ \textcolor{preprocessor}{\#if\ defined(RCC\_D2CCIP2R\_LPTIM1SEL)}}
\DoxyCodeLine{00653\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM1\_CLKSOURCE\_PCLK1\ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_LPTIM1SEL,\ \ RCC\_D2CCIP2R\_LPTIM1SEL\_Pos,\ \ 0x00000000U)}}
\DoxyCodeLine{00654\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM1\_CLKSOURCE\_PLL2P\ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_LPTIM1SEL,\ \ RCC\_D2CCIP2R\_LPTIM1SEL\_Pos,\ \ RCC\_D2CCIP2R\_LPTIM1SEL\_0)}}
\DoxyCodeLine{00655\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM1\_CLKSOURCE\_PLL3R\ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_LPTIM1SEL,\ \ RCC\_D2CCIP2R\_LPTIM1SEL\_Pos,\ \ RCC\_D2CCIP2R\_LPTIM1SEL\_1)}}
\DoxyCodeLine{00656\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM1\_CLKSOURCE\_LSE\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_LPTIM1SEL,\ \ RCC\_D2CCIP2R\_LPTIM1SEL\_Pos,\ \ RCC\_D2CCIP2R\_LPTIM1SEL\_0\ |\ RCC\_D2CCIP2R\_LPTIM1SEL\_1)}}
\DoxyCodeLine{00657\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM1\_CLKSOURCE\_LSI\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_LPTIM1SEL,\ \ RCC\_D2CCIP2R\_LPTIM1SEL\_Pos,\ \ RCC\_D2CCIP2R\_LPTIM1SEL\_2)}}
\DoxyCodeLine{00658\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM1\_CLKSOURCE\_CLKP\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP2,\ RCC\_D2CCIP2R\_LPTIM1SEL,\ \ RCC\_D2CCIP2R\_LPTIM1SEL\_Pos,\ \ RCC\_D2CCIP2R\_LPTIM1SEL\_0\ |\ RCC\_D2CCIP2R\_LPTIM1SEL\_2)}}
\DoxyCodeLine{00659\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{00660\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM1\_CLKSOURCE\_PCLK1\ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP2,\ RCC\_CDCCIP2R\_LPTIM1SEL,\ \ RCC\_CDCCIP2R\_LPTIM1SEL\_Pos,\ \ 0x00000000U)}}
\DoxyCodeLine{00661\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM1\_CLKSOURCE\_PLL2P\ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP2,\ RCC\_CDCCIP2R\_LPTIM1SEL,\ \ RCC\_CDCCIP2R\_LPTIM1SEL\_Pos,\ \ RCC\_CDCCIP2R\_LPTIM1SEL\_0)}}
\DoxyCodeLine{00662\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM1\_CLKSOURCE\_PLL3R\ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP2,\ RCC\_CDCCIP2R\_LPTIM1SEL,\ \ RCC\_CDCCIP2R\_LPTIM1SEL\_Pos,\ \ RCC\_CDCCIP2R\_LPTIM1SEL\_1)}}
\DoxyCodeLine{00663\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM1\_CLKSOURCE\_LSE\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP2,\ RCC\_CDCCIP2R\_LPTIM1SEL,\ \ RCC\_CDCCIP2R\_LPTIM1SEL\_Pos,\ \ RCC\_CDCCIP2R\_LPTIM1SEL\_0\ |\ RCC\_CDCCIP2R\_LPTIM1SEL\_1)}}
\DoxyCodeLine{00664\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM1\_CLKSOURCE\_LSI\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP2,\ RCC\_CDCCIP2R\_LPTIM1SEL,\ \ RCC\_CDCCIP2R\_LPTIM1SEL\_Pos,\ \ RCC\_CDCCIP2R\_LPTIM1SEL\_2)}}
\DoxyCodeLine{00665\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM1\_CLKSOURCE\_CLKP\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP2,\ RCC\_CDCCIP2R\_LPTIM1SEL,\ \ RCC\_CDCCIP2R\_LPTIM1SEL\_Pos,\ \ RCC\_CDCCIP2R\_LPTIM1SEL\_0\ |\ RCC\_CDCCIP2R\_LPTIM1SEL\_2)}}
\DoxyCodeLine{00666\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D2CCIP2R\_LPTIM1SEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00667\ \textcolor{preprocessor}{\#if\ defined(RCC\_D3CCIPR\_LPTIM2SEL)}}
\DoxyCodeLine{00668\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM2\_CLKSOURCE\_PCLK4\ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_LPTIM2SEL,\ \ \ RCC\_D3CCIPR\_LPTIM2SEL\_Pos,\ \ \ 0x00000000U)}}
\DoxyCodeLine{00669\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM2\_CLKSOURCE\_PLL2P\ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_LPTIM2SEL,\ \ \ RCC\_D3CCIPR\_LPTIM2SEL\_Pos,\ \ \ RCC\_D3CCIPR\_LPTIM2SEL\_0)}}
\DoxyCodeLine{00670\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM2\_CLKSOURCE\_PLL3R\ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_LPTIM2SEL,\ \ \ RCC\_D3CCIPR\_LPTIM2SEL\_Pos,\ \ \ RCC\_D3CCIPR\_LPTIM2SEL\_1)}}
\DoxyCodeLine{00671\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM2\_CLKSOURCE\_LSE\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_LPTIM2SEL,\ \ \ RCC\_D3CCIPR\_LPTIM2SEL\_Pos,\ \ \ RCC\_D3CCIPR\_LPTIM2SEL\_0\ |\ RCC\_D3CCIPR\_LPTIM2SEL\_1)}}
\DoxyCodeLine{00672\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM2\_CLKSOURCE\_LSI\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_LPTIM2SEL,\ \ \ RCC\_D3CCIPR\_LPTIM2SEL\_Pos,\ \ \ RCC\_D3CCIPR\_LPTIM2SEL\_2)}}
\DoxyCodeLine{00673\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM2\_CLKSOURCE\_CLKP\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_LPTIM2SEL,\ \ \ RCC\_D3CCIPR\_LPTIM2SEL\_Pos,\ \ \ RCC\_D3CCIPR\_LPTIM2SEL\_0\ |\ RCC\_D3CCIPR\_LPTIM2SEL\_2)}}
\DoxyCodeLine{00674\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{00675\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM2\_CLKSOURCE\_PCLK4\ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(SRDCCIP,\ \ RCC\_SRDCCIPR\_LPTIM2SEL,\ \ \ RCC\_SRDCCIPR\_LPTIM2SEL\_Pos,\ \ \ 0x00000000U)}}
\DoxyCodeLine{00676\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM2\_CLKSOURCE\_PLL2P\ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(SRDCCIP,\ \ RCC\_SRDCCIPR\_LPTIM2SEL,\ \ \ RCC\_SRDCCIPR\_LPTIM2SEL\_Pos,\ \ \ RCC\_SRDCCIPR\_LPTIM2SEL\_0)}}
\DoxyCodeLine{00677\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM2\_CLKSOURCE\_PLL3R\ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(SRDCCIP,\ \ RCC\_SRDCCIPR\_LPTIM2SEL,\ \ \ RCC\_SRDCCIPR\_LPTIM2SEL\_Pos,\ \ \ RCC\_SRDCCIPR\_LPTIM2SEL\_1)}}
\DoxyCodeLine{00678\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM2\_CLKSOURCE\_LSE\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(SRDCCIP,\ \ RCC\_SRDCCIPR\_LPTIM2SEL,\ \ \ RCC\_SRDCCIPR\_LPTIM2SEL\_Pos,\ \ \ RCC\_SRDCCIPR\_LPTIM2SEL\_0\ |\ RCC\_SRDCCIPR\_LPTIM2SEL\_1)}}
\DoxyCodeLine{00679\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM2\_CLKSOURCE\_LSI\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(SRDCCIP,\ \ RCC\_SRDCCIPR\_LPTIM2SEL,\ \ \ RCC\_SRDCCIPR\_LPTIM2SEL\_Pos,\ \ \ RCC\_SRDCCIPR\_LPTIM2SEL\_2)}}
\DoxyCodeLine{00680\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM2\_CLKSOURCE\_CLKP\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(SRDCCIP,\ \ RCC\_SRDCCIPR\_LPTIM2SEL,\ \ \ RCC\_SRDCCIPR\_LPTIM2SEL\_Pos,\ \ \ RCC\_SRDCCIPR\_LPTIM2SEL\_0\ |\ RCC\_SRDCCIPR\_LPTIM2SEL\_2)}}
\DoxyCodeLine{00681\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D3CCIPR\_LPTIM2SEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00682\ \textcolor{preprocessor}{\#if\ defined(RCC\_D3CCIPR\_LPTIM345SEL)}}
\DoxyCodeLine{00683\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM345\_CLKSOURCE\_PCLK4\ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_LPTIM345SEL,\ RCC\_D3CCIPR\_LPTIM345SEL\_Pos,\ 0x00000000U)}}
\DoxyCodeLine{00684\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM345\_CLKSOURCE\_PLL2P\ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_LPTIM345SEL,\ RCC\_D3CCIPR\_LPTIM345SEL\_Pos,\ RCC\_D3CCIPR\_LPTIM345SEL\_0)}}
\DoxyCodeLine{00685\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM345\_CLKSOURCE\_PLL3R\ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_LPTIM345SEL,\ RCC\_D3CCIPR\_LPTIM345SEL\_Pos,\ RCC\_D3CCIPR\_LPTIM345SEL\_1)}}
\DoxyCodeLine{00686\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM345\_CLKSOURCE\_LSE\ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_LPTIM345SEL,\ RCC\_D3CCIPR\_LPTIM345SEL\_Pos,\ RCC\_D3CCIPR\_LPTIM345SEL\_0\ |\ RCC\_D3CCIPR\_LPTIM345SEL\_1)}}
\DoxyCodeLine{00687\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM345\_CLKSOURCE\_LSI\ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_LPTIM345SEL,\ RCC\_D3CCIPR\_LPTIM345SEL\_Pos,\ RCC\_D3CCIPR\_LPTIM345SEL\_2)}}
\DoxyCodeLine{00688\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM345\_CLKSOURCE\_CLKP\ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_LPTIM345SEL,\ RCC\_D3CCIPR\_LPTIM345SEL\_Pos,\ RCC\_D3CCIPR\_LPTIM345SEL\_0\ |\ RCC\_D3CCIPR\_LPTIM345SEL\_2)}}
\DoxyCodeLine{00689\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{00690\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM345\_CLKSOURCE\_PCLK4\ \ \ \ \ \ \ \ LL\_CLKSOURCE(SRDCCIP,\ \ RCC\_SRDCCIPR\_LPTIM3SEL,\ RCC\_SRDCCIPR\_LPTIM3SEL\_Pos,\ 0x00000000U)}}
\DoxyCodeLine{00691\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM345\_CLKSOURCE\_PLL2P\ \ \ \ \ \ \ \ LL\_CLKSOURCE(SRDCCIP,\ \ RCC\_SRDCCIPR\_LPTIM3SEL,\ RCC\_SRDCCIPR\_LPTIM3SEL\_Pos,\ RCC\_SRDCCIPR\_LPTIM3SEL\_0)}}
\DoxyCodeLine{00692\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM345\_CLKSOURCE\_PLL3R\ \ \ \ \ \ \ \ LL\_CLKSOURCE(SRDCCIP,\ \ RCC\_SRDCCIPR\_LPTIM3SEL,\ RCC\_SRDCCIPR\_LPTIM3SEL\_Pos,\ RCC\_SRDCCIPR\_LPTIM3SEL\_1)}}
\DoxyCodeLine{00693\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM345\_CLKSOURCE\_LSE\ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(SRDCCIP,\ \ RCC\_SRDCCIPR\_LPTIM3SEL,\ RCC\_SRDCCIPR\_LPTIM3SEL\_Pos,\ RCC\_SRDCCIPR\_LPTIM3SEL\_0\ |\ RCC\_SRDCCIPR\_LPTIM3SEL\_1)}}
\DoxyCodeLine{00694\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM345\_CLKSOURCE\_LSI\ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(SRDCCIP,\ \ RCC\_SRDCCIPR\_LPTIM3SEL,\ RCC\_SRDCCIPR\_LPTIM3SEL\_Pos,\ RCC\_SRDCCIPR\_LPTIM3SEL\_2)}}
\DoxyCodeLine{00695\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM345\_CLKSOURCE\_CLKP\ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(SRDCCIP,\ \ RCC\_SRDCCIPR\_LPTIM3SEL,\ RCC\_SRDCCIPR\_LPTIM3SEL\_Pos,\ RCC\_SRDCCIPR\_LPTIM3SEL\_0\ |\ RCC\_SRDCCIPR\_LPTIM3SEL\_2)}}
\DoxyCodeLine{00696\ \textcolor{comment}{/*\ aliases*/}}
\DoxyCodeLine{00697\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM3\_CLKSOURCE\_PCLK4\ \ \ \ \ \ \ \ \ \ LL\_RCC\_LPTIM345\_CLKSOURCE\_PCLK4}}
\DoxyCodeLine{00698\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM3\_CLKSOURCE\_PLL2P\ \ \ \ \ \ \ \ \ \ LL\_RCC\_LPTIM345\_CLKSOURCE\_PLL2P}}
\DoxyCodeLine{00699\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM3\_CLKSOURCE\_PLL3R\ \ \ \ \ \ \ \ \ \ LL\_RCC\_LPTIM345\_CLKSOURCE\_PLL3R}}
\DoxyCodeLine{00700\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM3\_CLKSOURCE\_LSE\ \ \ \ \ \ \ \ \ \ \ \ LL\_RCC\_LPTIM345\_CLKSOURCE\_LSE}}
\DoxyCodeLine{00701\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM3\_CLKSOURCE\_LSI\ \ \ \ \ \ \ \ \ \ \ \ LL\_RCC\_LPTIM345\_CLKSOURCE\_LSI}}
\DoxyCodeLine{00702\ \textcolor{preprocessor}{\#define\ LL\_RCC\_LPTIM3\_CLKSOURCE\_CLKP\ \ \ \ \ \ \ \ \ \ \ LL\_RCC\_LPTIM345\_CLKSOURCE\_CLKP}}
\DoxyCodeLine{00703\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D3CCIPR\_LPTIM345SEL\ */}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{00707\ }
\DoxyCodeLine{00711\ \textcolor{preprocessor}{\#if\ defined(RCC\_D2CCIP1R\_SAI1SEL)}}
\DoxyCodeLine{00712\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI1\_CLKSOURCE\_PLL1Q\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP1,\ RCC\_D2CCIP1R\_SAI1SEL,\ \ RCC\_D2CCIP1R\_SAI1SEL\_Pos,\ \ 0x00000000U)}}
\DoxyCodeLine{00713\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI1\_CLKSOURCE\_PLL2P\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP1,\ RCC\_D2CCIP1R\_SAI1SEL,\ \ RCC\_D2CCIP1R\_SAI1SEL\_Pos,\ \ RCC\_D2CCIP1R\_SAI1SEL\_0)}}
\DoxyCodeLine{00714\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI1\_CLKSOURCE\_PLL3P\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP1,\ RCC\_D2CCIP1R\_SAI1SEL,\ \ RCC\_D2CCIP1R\_SAI1SEL\_Pos,\ \ RCC\_D2CCIP1R\_SAI1SEL\_1)}}
\DoxyCodeLine{00715\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI1\_CLKSOURCE\_I2S\_CKIN\ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP1,\ RCC\_D2CCIP1R\_SAI1SEL,\ \ RCC\_D2CCIP1R\_SAI1SEL\_Pos,\ \ RCC\_D2CCIP1R\_SAI1SEL\_0\ |\ RCC\_D2CCIP1R\_SAI1SEL\_1)}}
\DoxyCodeLine{00716\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI1\_CLKSOURCE\_CLKP\ \ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP1,\ RCC\_D2CCIP1R\_SAI1SEL,\ \ RCC\_D2CCIP1R\_SAI1SEL\_Pos,\ \ RCC\_D2CCIP1R\_SAI1SEL\_2)}}
\DoxyCodeLine{00717\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{00718\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI1\_CLKSOURCE\_PLL1Q\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP1,\ RCC\_CDCCIP1R\_SAI1SEL,\ \ RCC\_CDCCIP1R\_SAI1SEL\_Pos,\ \ 0x00000000U)}}
\DoxyCodeLine{00719\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI1\_CLKSOURCE\_PLL2P\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP1,\ RCC\_CDCCIP1R\_SAI1SEL,\ \ RCC\_CDCCIP1R\_SAI1SEL\_Pos,\ \ RCC\_CDCCIP1R\_SAI1SEL\_0)}}
\DoxyCodeLine{00720\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI1\_CLKSOURCE\_PLL3P\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP1,\ RCC\_CDCCIP1R\_SAI1SEL,\ \ RCC\_CDCCIP1R\_SAI1SEL\_Pos,\ \ RCC\_CDCCIP1R\_SAI1SEL\_1)}}
\DoxyCodeLine{00721\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI1\_CLKSOURCE\_I2S\_CKIN\ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP1,\ RCC\_CDCCIP1R\_SAI1SEL,\ \ RCC\_CDCCIP1R\_SAI1SEL\_Pos,\ \ RCC\_CDCCIP1R\_SAI1SEL\_0\ |\ RCC\_CDCCIP1R\_SAI1SEL\_1)}}
\DoxyCodeLine{00722\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI1\_CLKSOURCE\_CLKP\ \ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP1,\ RCC\_CDCCIP1R\_SAI1SEL,\ \ RCC\_CDCCIP1R\_SAI1SEL\_Pos,\ \ RCC\_CDCCIP1R\_SAI1SEL\_2)}}
\DoxyCodeLine{00723\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{00724\ \textcolor{preprocessor}{\#if\ defined(SAI3)}}
\DoxyCodeLine{00725\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI23\_CLKSOURCE\_PLL1Q\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP1,\ RCC\_D2CCIP1R\_SAI23SEL,\ RCC\_D2CCIP1R\_SAI23SEL\_Pos,\ 0x00000000U)}}
\DoxyCodeLine{00726\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI23\_CLKSOURCE\_PLL2P\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP1,\ RCC\_D2CCIP1R\_SAI23SEL,\ RCC\_D2CCIP1R\_SAI23SEL\_Pos,\ RCC\_D2CCIP1R\_SAI23SEL\_0)}}
\DoxyCodeLine{00727\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI23\_CLKSOURCE\_PLL3P\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP1,\ RCC\_D2CCIP1R\_SAI23SEL,\ RCC\_D2CCIP1R\_SAI23SEL\_Pos,\ RCC\_D2CCIP1R\_SAI23SEL\_1)}}
\DoxyCodeLine{00728\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI23\_CLKSOURCE\_I2S\_CKIN\ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP1,\ RCC\_D2CCIP1R\_SAI23SEL,\ RCC\_D2CCIP1R\_SAI23SEL\_Pos,\ RCC\_D2CCIP1R\_SAI23SEL\_0\ |\ RCC\_D2CCIP1R\_SAI23SEL\_1)}}
\DoxyCodeLine{00729\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI23\_CLKSOURCE\_CLKP\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D2CCIP1,\ RCC\_D2CCIP1R\_SAI23SEL,\ RCC\_D2CCIP1R\_SAI23SEL\_Pos,\ RCC\_D2CCIP1R\_SAI23SEL\_2)}}
\DoxyCodeLine{00730\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ SAI3\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00731\ \textcolor{preprocessor}{\#if\ defined(RCC\_CDCCIP1R\_SAI2ASEL)}}
\DoxyCodeLine{00732\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI2A\_CLKSOURCE\_PLL1Q\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP1,\ \ RCC\_CDCCIP1R\_SAI2ASEL,\ \ RCC\_CDCCIP1R\_SAI2ASEL\_Pos,\ \ 0x00000000U)}}
\DoxyCodeLine{00733\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI2A\_CLKSOURCE\_PLL2P\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP1,\ \ RCC\_CDCCIP1R\_SAI2ASEL,\ \ RCC\_CDCCIP1R\_SAI2ASEL\_Pos,\ \ RCC\_CDCCIP1R\_SAI2ASEL\_0)}}
\DoxyCodeLine{00734\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI2A\_CLKSOURCE\_PLL3P\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP1,\ \ RCC\_CDCCIP1R\_SAI2ASEL,\ \ RCC\_CDCCIP1R\_SAI2ASEL\_Pos,\ \ RCC\_CDCCIP1R\_SAI2ASEL\_1)}}
\DoxyCodeLine{00735\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI2A\_CLKSOURCE\_I2S\_CKIN\ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP1,\ \ RCC\_CDCCIP1R\_SAI2ASEL,\ \ RCC\_CDCCIP1R\_SAI2ASEL\_Pos,\ \ RCC\_CDCCIP1R\_SAI2ASEL\_0\ |\ RCC\_CDCCIP1R\_SAI2ASEL\_1)}}
\DoxyCodeLine{00736\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI2A\_CLKSOURCE\_CLKP\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP1,\ \ RCC\_CDCCIP1R\_SAI2ASEL,\ \ RCC\_CDCCIP1R\_SAI2ASEL\_Pos,\ \ RCC\_CDCCIP1R\_SAI2ASEL\_2)}}
\DoxyCodeLine{00737\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI2A\_CLKSOURCE\_SPDIF\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP1,\ \ RCC\_CDCCIP1R\_SAI2ASEL,\ \ RCC\_CDCCIP1R\_SAI2ASEL\_Pos,\ \ RCC\_CDCCIP1R\_SAI2ASEL\_0\ |\ RCC\_CDCCIP1R\_SAI2ASEL\_2)}}
\DoxyCodeLine{00738\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_CDCCIP1R\_SAI2ASEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00739\ \textcolor{preprocessor}{\#if\ defined(RCC\_CDCCIP1R\_SAI2BSEL)}}
\DoxyCodeLine{00740\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI2B\_CLKSOURCE\_PLL1Q\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP1,\ \ RCC\_CDCCIP1R\_SAI2BSEL,\ \ RCC\_CDCCIP1R\_SAI2BSEL\_Pos,\ \ 0x00000000U)}}
\DoxyCodeLine{00741\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI2B\_CLKSOURCE\_PLL2P\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP1,\ \ RCC\_CDCCIP1R\_SAI2BSEL,\ \ RCC\_CDCCIP1R\_SAI2BSEL\_Pos,\ \ RCC\_CDCCIP1R\_SAI2BSEL\_0)}}
\DoxyCodeLine{00742\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI2B\_CLKSOURCE\_PLL3P\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP1,\ \ RCC\_CDCCIP1R\_SAI2BSEL,\ \ RCC\_CDCCIP1R\_SAI2BSEL\_Pos,\ \ RCC\_CDCCIP1R\_SAI2BSEL\_1)}}
\DoxyCodeLine{00743\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI2B\_CLKSOURCE\_I2S\_CKIN\ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP1,\ \ RCC\_CDCCIP1R\_SAI2BSEL,\ \ RCC\_CDCCIP1R\_SAI2BSEL\_Pos,\ \ RCC\_CDCCIP1R\_SAI2BSEL\_0\ |\ RCC\_CDCCIP1R\_SAI2BSEL\_1)}}
\DoxyCodeLine{00744\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI2B\_CLKSOURCE\_CLKP\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP1,\ \ RCC\_CDCCIP1R\_SAI2BSEL,\ \ RCC\_CDCCIP1R\_SAI2BSEL\_Pos,\ \ RCC\_CDCCIP1R\_SAI2BSEL\_2)}}
\DoxyCodeLine{00745\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI2B\_CLKSOURCE\_SPDIF\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(CDCCIP1,\ \ RCC\_CDCCIP1R\_SAI2BSEL,\ \ RCC\_CDCCIP1R\_SAI2BSEL\_Pos,\ \ RCC\_CDCCIP1R\_SAI2BSEL\_0\ |\ RCC\_CDCCIP1R\_SAI2BSEL\_2)}}
\DoxyCodeLine{00746\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_CDCCIP1R\_SAI2BSEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00747\ \textcolor{preprocessor}{\#if\ defined(SAI4\_Block\_A)}}
\DoxyCodeLine{00748\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI4A\_CLKSOURCE\_PLL1Q\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_SAI4ASEL,\ \ RCC\_D3CCIPR\_SAI4ASEL\_Pos,\ \ 0x00000000U)}}
\DoxyCodeLine{00749\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI4A\_CLKSOURCE\_PLL2P\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_SAI4ASEL,\ \ RCC\_D3CCIPR\_SAI4ASEL\_Pos,\ \ RCC\_D3CCIPR\_SAI4ASEL\_0)}}
\DoxyCodeLine{00750\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI4A\_CLKSOURCE\_PLL3P\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_SAI4ASEL,\ \ RCC\_D3CCIPR\_SAI4ASEL\_Pos,\ \ RCC\_D3CCIPR\_SAI4ASEL\_1)}}
\DoxyCodeLine{00751\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI4A\_CLKSOURCE\_I2S\_CKIN\ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_SAI4ASEL,\ \ RCC\_D3CCIPR\_SAI4ASEL\_Pos,\ \ RCC\_D3CCIPR\_SAI4ASEL\_0\ |\ RCC\_D3CCIPR\_SAI4ASEL\_1)}}
\DoxyCodeLine{00752\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI4A\_CLKSOURCE\_CLKP\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_SAI4ASEL,\ \ RCC\_D3CCIPR\_SAI4ASEL\_Pos,\ \ RCC\_D3CCIPR\_SAI4ASEL\_2)}}
\DoxyCodeLine{00753\ \textcolor{preprocessor}{\#if\ defined(RCC\_VER\_3\_0)}}
\DoxyCodeLine{00754\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI4A\_CLKSOURCE\_SPDIF\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_SAI4ASEL,\ \ RCC\_D3CCIPR\_SAI4ASEL\_Pos,\ \ RCC\_D3CCIPR\_SAI4ASEL\_2\ |\ RCC\_D3CCIPR\_SAI4ASEL\_0)}}
\DoxyCodeLine{00755\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_VER\_3\_0\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00756\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ SAI4\_Block\_A\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00757\ \textcolor{preprocessor}{\#if\ defined(SAI4\_Block\_B)}}
\DoxyCodeLine{00758\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI4B\_CLKSOURCE\_PLL1Q\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_SAI4BSEL,\ \ RCC\_D3CCIPR\_SAI4BSEL\_Pos,\ \ 0x00000000U)}}
\DoxyCodeLine{00759\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI4B\_CLKSOURCE\_PLL2P\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_SAI4BSEL,\ \ RCC\_D3CCIPR\_SAI4BSEL\_Pos,\ \ RCC\_D3CCIPR\_SAI4BSEL\_0)}}
\DoxyCodeLine{00760\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI4B\_CLKSOURCE\_PLL3P\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_SAI4BSEL,\ \ RCC\_D3CCIPR\_SAI4BSEL\_Pos,\ \ RCC\_D3CCIPR\_SAI4BSEL\_1)}}
\DoxyCodeLine{00761\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI4B\_CLKSOURCE\_I2S\_CKIN\ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_SAI4BSEL,\ \ RCC\_D3CCIPR\_SAI4BSEL\_Pos,\ \ RCC\_D3CCIPR\_SAI4BSEL\_0\ |\ RCC\_D3CCIPR\_SAI4BSEL\_1)}}
\DoxyCodeLine{00762\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI4B\_CLKSOURCE\_CLKP\ \ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_SAI4BSEL,\ \ RCC\_D3CCIPR\_SAI4BSEL\_Pos,\ \ RCC\_D3CCIPR\_SAI4BSEL\_2)}}
\DoxyCodeLine{00763\ \textcolor{preprocessor}{\#if\ defined(RCC\_VER\_3\_0)}}
\DoxyCodeLine{00764\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SAI4B\_CLKSOURCE\_SPDIF\ \ \ \ \ \ \ \ \ \ \ LL\_CLKSOURCE(D3CCIP,\ \ RCC\_D3CCIPR\_SAI4BSEL,\ \ RCC\_D3CCIPR\_SAI4BSEL\_Pos,\ \ RCC\_D3CCIPR\_SAI4BSEL\_2\ |\ RCC\_D3CCIPR\_SAI4BSEL\_0)}}
\DoxyCodeLine{00765\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_VER\_3\_0\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00766\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ SAI4\_Block\_B\ */}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{00770\ }
\DoxyCodeLine{00774\ \textcolor{preprocessor}{\#if\ defined(RCC\_D1CCIPR\_SDMMCSEL)}}
\DoxyCodeLine{00775\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SDMMC\_CLKSOURCE\_PLL1Q\ \ \ \ \ \ \ \ \ \ \ (0x00000000U)}}
\DoxyCodeLine{00776\ \textcolor{preprocessor}{\#define\ LL\_RCC\_SDMMC\_CLKSOURCE\_PLL2R\ \ \ \ \ \ \ \ \ \ \ (RCC\_D1CCIPR\_SDMMCSEL)}}
\DoxyCodeLine{00777\ \textcolor{preprocessor}{\#else}}
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\DoxyCodeLine{01614\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_HSE\_EnableCSS(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{01626\ \ \ SET\_BIT(RCC-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa3288090671af5a959aae4d7f7696d55}{RCC\_CR\_HSEBYP}});}
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\DoxyCodeLine{01634\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_HSE\_DisableBypass(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{01637\ \}}
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\DoxyCodeLine{01639\ \textcolor{preprocessor}{\#if\ defined(RCC\_CR\_HSEEXT)}\textcolor{preprocessor}{}}
\DoxyCodeLine{01645\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_HSE\_SelectAnalogClock(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{01647\ \ \ CLEAR\_BIT(RCC-\/>CR,\ RCC\_CR\_HSEEXT);}
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\DoxyCodeLine{01649\ }
\DoxyCodeLine{01655\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_HSE\_SelectDigitalClock(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{01658\ \}}
\DoxyCodeLine{01659\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_CR\_HSEEXT\ */}\textcolor{preprocessor}{}}
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\DoxyCodeLine{01676\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_HSE\_Disable(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{01749\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_HSI\_SetDivider(uint32\_t\ Divider)}
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\DoxyCodeLine{02126\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_WWDG1\_EnableSystemReset(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{02138\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(RCC-\/>GCR,\ RCC\_GCR\_WW1RSC)\ ==\ RCC\_GCR\_WW1RSC)\ ?\ 1UL\ :\ 0UL);}
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\DoxyCodeLine{02140\ \textcolor{preprocessor}{\#endif\ \ }\textcolor{comment}{/*\ RCC\_GCR\_WW1RSC\ */}\textcolor{preprocessor}{}}
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\DoxyCodeLine{02158\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_WWDG2\_IsSystemReset(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{02160\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(RCC-\/>GCR,\ RCC\_GCR\_WW2RSC)\ ==\ RCC\_GCR\_WW2RSC)\ ?\ 1UL\ :\ 0UL);}
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\DoxyCodeLine{02162\ \textcolor{preprocessor}{\#endif\ \ }\textcolor{comment}{/*DUAL\_CORE*/}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{02177\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_ForceCM4Boot(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{02189\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(RCC-\/>GCR,\ RCC\_GCR\_BOOT\_C2)\ ==\ RCC\_GCR\_BOOT\_C2)\ ?\ 1UL\ :\ 0UL);}
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\DoxyCodeLine{02211\ }
\DoxyCodeLine{02215\ \textcolor{preprocessor}{\#endif\ \ }\textcolor{comment}{/*DUAL\_CORE*/}\textcolor{preprocessor}{}}
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\DoxyCodeLine{02220\ }
\DoxyCodeLine{02228\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_LSE\_EnableCSS(\textcolor{keywordtype}{void})}
\DoxyCodeLine{02229\ \{}
\DoxyCodeLine{02230\ \ \ SET\_BIT(RCC-\/>BDCR,\ RCC\_BDCR\_LSECSSON);}
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\DoxyCodeLine{02232\ }
\DoxyCodeLine{02238\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_LSE\_IsFailureDetected(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{02240\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(RCC-\/>BDCR,\ RCC\_BDCR\_LSECSSD)\ ==\ (RCC\_BDCR\_LSECSSD))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02241\ \}}
\DoxyCodeLine{02242\ }
\DoxyCodeLine{02248\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_LSE\_Enable(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{02252\ }
\DoxyCodeLine{02258\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_LSE\_Disable(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{02262\ }
\DoxyCodeLine{02268\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_LSE\_EnableBypass(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{02282\ }
\DoxyCodeLine{02283\ \textcolor{preprocessor}{\#if\ defined(RCC\_BDCR\_LSEEXT)}\textcolor{preprocessor}{}}
\DoxyCodeLine{02291\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_LSE\_SelectDigitalClock(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{02303\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_LSE\_SelectAnalogClock(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{02307\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_BDCR\_LSEEXT\ */}\textcolor{preprocessor}{}}
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\DoxyCodeLine{02320\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_LSE\_SetDriveCapability(uint32\_t\ LSEDrive)}
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\DoxyCodeLine{02334\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_LSE\_GetDriveCapability(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{02347\ \}}
\DoxyCodeLine{02348\ }
\DoxyCodeLine{02352\ }
\DoxyCodeLine{02356\ }
\DoxyCodeLine{02362\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_LSI\_Enable(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{02385\ \}}
\DoxyCodeLine{02386\ }
\DoxyCodeLine{02390\ }
\DoxyCodeLine{02394\ }
\DoxyCodeLine{02405\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetSysClkSource(uint32\_t\ Source)}
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\DoxyCodeLine{02423\ }
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\DoxyCodeLine{02473\ }
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\DoxyCodeLine{02496\ \}}
\DoxyCodeLine{02497\ }
\DoxyCodeLine{02513\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetAHBPrescaler(uint32\_t\ Prescaler)}
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\DoxyCodeLine{02520\ \}}
\DoxyCodeLine{02521\ }
\DoxyCodeLine{02533\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetAPB1Prescaler(uint32\_t\ Prescaler)}
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\DoxyCodeLine{02540\ \}}
\DoxyCodeLine{02541\ }
\DoxyCodeLine{02553\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetAPB2Prescaler(uint32\_t\ Prescaler)}
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\DoxyCodeLine{02560\ \}}
\DoxyCodeLine{02561\ }
\DoxyCodeLine{02573\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetAPB3Prescaler(uint32\_t\ Prescaler)}
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\DoxyCodeLine{02580\ \}}
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\DoxyCodeLine{02601\ }
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\DoxyCodeLine{02624\ }
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\DoxyCodeLine{02646\ \}}
\DoxyCodeLine{02647\ }
\DoxyCodeLine{02658\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetAPB1Prescaler(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{02661\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>D2CFGR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gadfc0b703ac99ca7cbbb12cd785b2d836}{RCC\_D2CFGR\_D2PPRE1}}));}
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\DoxyCodeLine{02666\ }
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\DoxyCodeLine{02680\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>D2CFGR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gab37ebc780e5ce2006ace8919baaae06a}{RCC\_D2CFGR\_D2PPRE2}}));}
\DoxyCodeLine{02681\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{02682\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>CDCFGR2,\ RCC\_CDCFGR2\_CDPPRE2));}
\DoxyCodeLine{02683\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D2CFGR\_D2PPRE2\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02684\ \}}
\DoxyCodeLine{02685\ }
\DoxyCodeLine{02696\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetAPB3Prescaler(\textcolor{keywordtype}{void})}
\DoxyCodeLine{02697\ \{}
\DoxyCodeLine{02698\ \textcolor{preprocessor}{\#if\ defined(RCC\_D1CFGR\_D1PPRE)}}
\DoxyCodeLine{02699\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>D1CFGR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga156ad49f4491b54e9c1bd6029814a03d}{RCC\_D1CFGR\_D1PPRE}}));}
\DoxyCodeLine{02700\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{02701\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>CDCFGR1,\ RCC\_CDCFGR1\_CDPPRE));}
\DoxyCodeLine{02702\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D1CFGR\_D1PPRE\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02703\ \}}
\DoxyCodeLine{02704\ }
\DoxyCodeLine{02715\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetAPB4Prescaler(\textcolor{keywordtype}{void})}
\DoxyCodeLine{02716\ \{}
\DoxyCodeLine{02717\ \textcolor{preprocessor}{\#if\ defined(RCC\_D3CFGR\_D3PPRE)}}
\DoxyCodeLine{02718\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>D3CFGR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga8c6b1922986a9444c5835cb0f9de4be5}{RCC\_D3CFGR\_D3PPRE}}));}
\DoxyCodeLine{02719\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{02720\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>SRDCFGR,\ RCC\_SRDCFGR\_SRDPPRE));}
\DoxyCodeLine{02721\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D3CFGR\_D3PPRE\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02722\ \}}
\DoxyCodeLine{02723\ }
\DoxyCodeLine{02727\ }
\DoxyCodeLine{02731\ }
\DoxyCodeLine{02783\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_ConfigMCO(uint32\_t\ MCOxSource,\ uint32\_t\ MCOxPrescaler)}
\DoxyCodeLine{02784\ \{}
\DoxyCodeLine{02785\ \ \ MODIFY\_REG(RCC-\/>CFGR,\ (MCOxSource\ <<\ 16U)\ |\ (MCOxPrescaler\ <<\ 16U),\ (MCOxSource\ \&\ 0xFFFF0000U)\ |\ (MCOxPrescaler\ \&\ 0xFFFF0000U));}
\DoxyCodeLine{02786\ \}}
\DoxyCodeLine{02787\ }
\DoxyCodeLine{02791\ }
\DoxyCodeLine{02795\ }
\DoxyCodeLine{02895\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetClockSource(uint32\_t\ ClkSource)}
\DoxyCodeLine{02896\ \{}
\DoxyCodeLine{02897\ \textcolor{preprocessor}{\#if\ defined(RCC\_D1CCIPR\_FMCSEL)}}
\DoxyCodeLine{02898\ \ \ uint32\_t\ *pReg\ =\ (uint32\_t\ *)((uint32\_t)\&RCC-\/>D1CCIPR\ +\ LL\_CLKSOURCE\_REG(ClkSource));}
\DoxyCodeLine{02899\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{02900\ \ \ uint32\_t\ *pReg\ =\ (uint32\_t\ *)((uint32\_t)\&RCC-\/>CDCCIPR\ +\ LL\_CLKSOURCE\_REG(ClkSource));}
\DoxyCodeLine{02901\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ \ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02902\ \ \ MODIFY\_REG(*pReg,\ LL\_CLKSOURCE\_MASK(ClkSource),\ LL\_CLKSOURCE\_CONFIG(ClkSource));}
\DoxyCodeLine{02903\ \}}
\DoxyCodeLine{02904\ }
\DoxyCodeLine{02924\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetUSARTClockSource(uint32\_t\ ClkSource)}
\DoxyCodeLine{02925\ \{}
\DoxyCodeLine{02926\ \ \ LL\_RCC\_SetClockSource(ClkSource);}
\DoxyCodeLine{02927\ \}}
\DoxyCodeLine{02928\ }
\DoxyCodeLine{02941\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetLPUARTClockSource(uint32\_t\ ClkSource)}
\DoxyCodeLine{02942\ \{}
\DoxyCodeLine{02943\ \textcolor{preprocessor}{\#if\ defined(RCC\_D3CCIPR\_LPUART1SEL)}}
\DoxyCodeLine{02944\ \ \ MODIFY\_REG(RCC-\/>D3CCIPR,\ RCC\_D3CCIPR\_LPUART1SEL,\ ClkSource);}
\DoxyCodeLine{02945\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{02946\ \ \ MODIFY\_REG(RCC-\/>SRDCCIPR,\ RCC\_SRDCCIPR\_LPUART1SEL,\ ClkSource);}
\DoxyCodeLine{02947\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D3CCIPR\_LPUART1SEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02948\ \}}
\DoxyCodeLine{02949\ }
\DoxyCodeLine{02965\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetI2CClockSource(uint32\_t\ ClkSource)}
\DoxyCodeLine{02966\ \{}
\DoxyCodeLine{02967\ \ \ LL\_RCC\_SetClockSource(ClkSource);}
\DoxyCodeLine{02968\ \}}
\DoxyCodeLine{02969\ }
\DoxyCodeLine{02996\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetLPTIMClockSource(uint32\_t\ ClkSource)}
\DoxyCodeLine{02997\ \{}
\DoxyCodeLine{02998\ \ \ LL\_RCC\_SetClockSource(ClkSource);}
\DoxyCodeLine{02999\ \}}
\DoxyCodeLine{03000\ }
\DoxyCodeLine{03045\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetSAIClockSource(uint32\_t\ ClkSource)}
\DoxyCodeLine{03046\ \{}
\DoxyCodeLine{03047\ \ \ LL\_RCC\_SetClockSource(ClkSource);}
\DoxyCodeLine{03048\ \}}
\DoxyCodeLine{03049\ }
\DoxyCodeLine{03058\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetSDMMCClockSource(uint32\_t\ ClkSource)}
\DoxyCodeLine{03059\ \{}
\DoxyCodeLine{03060\ \textcolor{preprocessor}{\#if\ defined(RCC\_D1CCIPR\_SDMMCSEL)}}
\DoxyCodeLine{03061\ \ \ MODIFY\_REG(RCC-\/>D1CCIPR,\ RCC\_D1CCIPR\_SDMMCSEL,\ ClkSource);}
\DoxyCodeLine{03062\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03063\ \ \ MODIFY\_REG(RCC-\/>CDCCIPR,\ RCC\_CDCCIPR\_SDMMCSEL,\ ClkSource);}
\DoxyCodeLine{03064\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D1CCIPR\_SDMMCSEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03065\ \}}
\DoxyCodeLine{03066\ }
\DoxyCodeLine{03077\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetRNGClockSource(uint32\_t\ ClkSource)}
\DoxyCodeLine{03078\ \{}
\DoxyCodeLine{03079\ \textcolor{preprocessor}{\#if\ defined(RCC\_D2CCIP2R\_RNGSEL)}}
\DoxyCodeLine{03080\ \ \ MODIFY\_REG(RCC-\/>D2CCIP2R,\ RCC\_D2CCIP2R\_RNGSEL,\ ClkSource);}
\DoxyCodeLine{03081\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03082\ \ \ MODIFY\_REG(RCC-\/>CDCCIP2R,\ RCC\_CDCCIP2R\_RNGSEL,\ ClkSource);}
\DoxyCodeLine{03083\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D2CCIP2R\_RNGSEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03084\ \}}
\DoxyCodeLine{03085\ }
\DoxyCodeLine{03096\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetUSBClockSource(uint32\_t\ ClkSource)}
\DoxyCodeLine{03097\ \{}
\DoxyCodeLine{03098\ \textcolor{preprocessor}{\#if\ defined(RCC\_D2CCIP2R\_USBSEL)}}
\DoxyCodeLine{03099\ \ \ MODIFY\_REG(RCC-\/>D2CCIP2R,\ RCC\_D2CCIP2R\_USBSEL,\ ClkSource);}
\DoxyCodeLine{03100\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03101\ \ \ MODIFY\_REG(RCC-\/>CDCCIP2R,\ RCC\_CDCCIP2R\_USBSEL,\ ClkSource);}
\DoxyCodeLine{03102\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D2CCIP2R\_USBSEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03103\ \}}
\DoxyCodeLine{03104\ }
\DoxyCodeLine{03114\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetCECClockSource(uint32\_t\ ClkSource)}
\DoxyCodeLine{03115\ \{}
\DoxyCodeLine{03116\ \textcolor{preprocessor}{\#if\ defined(RCC\_D2CCIP2R\_CECSEL)}}
\DoxyCodeLine{03117\ \ \ MODIFY\_REG(RCC-\/>D2CCIP2R,\ RCC\_D2CCIP2R\_CECSEL,\ ClkSource);}
\DoxyCodeLine{03118\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03119\ \ \ MODIFY\_REG(RCC-\/>CDCCIP2R,\ RCC\_CDCCIP2R\_CECSEL,\ ClkSource);}
\DoxyCodeLine{03120\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D2CCIP2R\_CECSEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03121\ \}}
\DoxyCodeLine{03122\ }
\DoxyCodeLine{03123\ \textcolor{preprocessor}{\#if\ defined(DSI)}\textcolor{preprocessor}{}}
\DoxyCodeLine{03132\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetDSIClockSource(uint32\_t\ ClkSource)}
\DoxyCodeLine{03133\ \{}
\DoxyCodeLine{03134\ \ \ MODIFY\_REG(RCC-\/>D1CCIPR,\ RCC\_D1CCIPR\_DSISEL,\ ClkSource);}
\DoxyCodeLine{03135\ \}}
\DoxyCodeLine{03136\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ DSI\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03137\ }
\DoxyCodeLine{03146\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetDFSDMClockSource(uint32\_t\ ClkSource)}
\DoxyCodeLine{03147\ \{}
\DoxyCodeLine{03148\ \textcolor{preprocessor}{\#if\ defined(RCC\_D2CCIP1R\_DFSDM1SEL)}}
\DoxyCodeLine{03149\ \ \ MODIFY\_REG(RCC-\/>D2CCIP1R,\ RCC\_D2CCIP1R\_DFSDM1SEL,\ ClkSource);}
\DoxyCodeLine{03150\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03151\ \ \ MODIFY\_REG(RCC-\/>CDCCIP1R,\ RCC\_CDCCIP1R\_DFSDM1SEL,\ ClkSource);}
\DoxyCodeLine{03152\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D2CCIP1R\_DFSDM1SEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03153\ \}}
\DoxyCodeLine{03154\ }
\DoxyCodeLine{03155\ \textcolor{preprocessor}{\#if\ defined(DFSDM2\_BASE)}\textcolor{preprocessor}{}}
\DoxyCodeLine{03164\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetDFSDM2ClockSource(uint32\_t\ ClkSource)}
\DoxyCodeLine{03165\ \{}
\DoxyCodeLine{03166\ \ \ MODIFY\_REG(RCC-\/>SRDCCIPR,\ RCC\_SRDCCIPR\_DFSDM2SEL,\ ClkSource);}
\DoxyCodeLine{03167\ \}}
\DoxyCodeLine{03168\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ DFSDM2\_BASE\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03169\ }
\DoxyCodeLine{03180\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetFMCClockSource(uint32\_t\ ClkSource)}
\DoxyCodeLine{03181\ \{}
\DoxyCodeLine{03182\ \textcolor{preprocessor}{\#if\ defined(RCC\_D1CCIPR\_FMCSEL)}}
\DoxyCodeLine{03183\ \ \ MODIFY\_REG(RCC-\/>D1CCIPR,\ RCC\_D1CCIPR\_FMCSEL,\ ClkSource);}
\DoxyCodeLine{03184\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03185\ \ \ MODIFY\_REG(RCC-\/>CDCCIPR,\ RCC\_CDCCIPR\_FMCSEL,\ ClkSource);}
\DoxyCodeLine{03186\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D1CCIPR\_FMCSEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03187\ \}}
\DoxyCodeLine{03188\ }
\DoxyCodeLine{03189\ \textcolor{preprocessor}{\#if\ defined(QUADSPI)}\textcolor{preprocessor}{}}
\DoxyCodeLine{03200\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetQSPIClockSource(uint32\_t\ ClkSource)}
\DoxyCodeLine{03201\ \{}
\DoxyCodeLine{03202\ \ \ MODIFY\_REG(RCC-\/>D1CCIPR,\ RCC\_D1CCIPR\_QSPISEL,\ ClkSource);}
\DoxyCodeLine{03203\ \}}
\DoxyCodeLine{03204\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ QUADSPI\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03205\ }
\DoxyCodeLine{03206\ \textcolor{preprocessor}{\#if\ defined(OCTOSPI1)\ ||\ defined(OCTOSPI2)}\textcolor{preprocessor}{}}
\DoxyCodeLine{03217\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetOSPIClockSource(uint32\_t\ ClkSource)}
\DoxyCodeLine{03218\ \{}
\DoxyCodeLine{03219\ \textcolor{preprocessor}{\#if\ defined(RCC\_D1CCIPR\_OCTOSPISEL)}}
\DoxyCodeLine{03220\ \ \ MODIFY\_REG(RCC-\/>D1CCIPR,\ RCC\_D1CCIPR\_OCTOSPISEL,\ ClkSource);}
\DoxyCodeLine{03221\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03222\ \ \ MODIFY\_REG(RCC-\/>CDCCIPR,\ RCC\_CDCCIPR\_OCTOSPISEL,\ ClkSource);}
\DoxyCodeLine{03223\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D1CCIPR\_OCTOSPISEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03224\ \}}
\DoxyCodeLine{03225\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ OCTOSPI1\ ||\ OCTOSPI2\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03226\ }
\DoxyCodeLine{03236\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetCLKPClockSource(uint32\_t\ ClkSource)}
\DoxyCodeLine{03237\ \{}
\DoxyCodeLine{03238\ \textcolor{preprocessor}{\#if\ defined(RCC\_D1CCIPR\_CKPERSEL)}}
\DoxyCodeLine{03239\ \ \ MODIFY\_REG(RCC-\/>D1CCIPR,\ RCC\_D1CCIPR\_CKPERSEL,\ ClkSource);}
\DoxyCodeLine{03240\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03241\ \ \ MODIFY\_REG(RCC-\/>CDCCIPR,\ RCC\_CDCCIPR\_CKPERSEL,\ ClkSource);}
\DoxyCodeLine{03242\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D1CCIPR\_CKPERSEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03243\ \}}
\DoxyCodeLine{03244\ }
\DoxyCodeLine{03273\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetSPIClockSource(uint32\_t\ ClkSource)}
\DoxyCodeLine{03274\ \{}
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\DoxyCodeLine{03276\ \}}
\DoxyCodeLine{03277\ }
\DoxyCodeLine{03288\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetSPDIFClockSource(uint32\_t\ ClkSource)}
\DoxyCodeLine{03289\ \{}
\DoxyCodeLine{03290\ \textcolor{preprocessor}{\#if\ defined(RCC\_D2CCIP1R\_SPDIFSEL)}}
\DoxyCodeLine{03291\ \ \ MODIFY\_REG(RCC-\/>D2CCIP1R,\ RCC\_D2CCIP1R\_SPDIFSEL,\ ClkSource);}
\DoxyCodeLine{03292\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03293\ \ \ MODIFY\_REG(RCC-\/>CDCCIP1R,\ RCC\_CDCCIP1R\_SPDIFSEL,\ ClkSource);}
\DoxyCodeLine{03294\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D2CCIP1R\_SPDIFSEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03295\ \}}
\DoxyCodeLine{03296\ }
\DoxyCodeLine{03306\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetFDCANClockSource(uint32\_t\ ClkSource)}
\DoxyCodeLine{03307\ \{}
\DoxyCodeLine{03308\ \textcolor{preprocessor}{\#if\ defined(RCC\_D2CCIP1R\_FDCANSEL)}}
\DoxyCodeLine{03309\ \ \ MODIFY\_REG(RCC-\/>D2CCIP1R,\ RCC\_D2CCIP1R\_FDCANSEL,\ ClkSource);}
\DoxyCodeLine{03310\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03311\ \ \ MODIFY\_REG(RCC-\/>CDCCIP1R,\ RCC\_CDCCIP1R\_FDCANSEL,\ ClkSource);}
\DoxyCodeLine{03312\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D2CCIP1R\_FDCANSEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03313\ \}}
\DoxyCodeLine{03314\ }
\DoxyCodeLine{03323\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetSWPClockSource(uint32\_t\ ClkSource)}
\DoxyCodeLine{03324\ \{}
\DoxyCodeLine{03325\ \textcolor{preprocessor}{\#if\ defined(RCC\_D2CCIP1R\_SWPSEL)}}
\DoxyCodeLine{03326\ \ \ MODIFY\_REG(RCC-\/>D2CCIP1R,\ RCC\_D2CCIP1R\_SWPSEL,\ ClkSource);}
\DoxyCodeLine{03327\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03328\ \ \ MODIFY\_REG(RCC-\/>CDCCIP1R,\ RCC\_CDCCIP1R\_SWPSEL,\ ClkSource);}
\DoxyCodeLine{03329\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D2CCIP1R\_SWPSEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03330\ \}}
\DoxyCodeLine{03331\ }
\DoxyCodeLine{03341\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetADCClockSource(uint32\_t\ ClkSource)}
\DoxyCodeLine{03342\ \{}
\DoxyCodeLine{03343\ \textcolor{preprocessor}{\#if\ defined(RCC\_D3CCIPR\_ADCSEL)}}
\DoxyCodeLine{03344\ \ \ MODIFY\_REG(RCC-\/>D3CCIPR,\ RCC\_D3CCIPR\_ADCSEL,\ ClkSource);}
\DoxyCodeLine{03345\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03346\ \ \ MODIFY\_REG(RCC-\/>SRDCCIPR,\ RCC\_SRDCCIPR\_ADCSEL,\ ClkSource);}
\DoxyCodeLine{03347\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D3CCIPR\_ADCSEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03348\ \}}
\DoxyCodeLine{03349\ }
\DoxyCodeLine{03466\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetClockSource(uint32\_t\ Periph)}
\DoxyCodeLine{03467\ \{}
\DoxyCodeLine{03468\ \textcolor{preprocessor}{\#if\ defined(RCC\_D1CCIPR\_FMCSEL)}}
\DoxyCodeLine{03469\ \ \ \textcolor{keyword}{const}\ uint32\_t\ *pReg\ =\ (uint32\_t\ *)((uint32\_t)((uint32\_t)(\&RCC-\/>D1CCIPR)\ +\ LL\_CLKSOURCE\_REG(Periph)));}
\DoxyCodeLine{03470\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03471\ \ \ \textcolor{keyword}{const}\ uint32\_t\ *pReg\ =\ (uint32\_t\ *)((uint32\_t)((uint32\_t)(\&RCC-\/>CDCCIPR)\ +\ LL\_CLKSOURCE\_REG(Periph)));}
\DoxyCodeLine{03472\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D1CCIPR\_FMCSEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03473\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(Periph\ |\ (((READ\_BIT(*pReg,\ LL\_CLKSOURCE\_MASK(Periph)))\ >>\ LL\_CLKSOURCE\_SHIFT(Periph))\ <<\ LL\_RCC\_CONFIG\_SHIFT));}
\DoxyCodeLine{03474\ \}}
\DoxyCodeLine{03475\ }
\DoxyCodeLine{03497\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetUSARTClockSource(uint32\_t\ Periph)}
\DoxyCodeLine{03498\ \{}
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\DoxyCodeLine{03500\ \}}
\DoxyCodeLine{03501\ }
\DoxyCodeLine{03515\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetLPUARTClockSource(uint32\_t\ Periph)}
\DoxyCodeLine{03516\ \{}
\DoxyCodeLine{03517\ \ \ UNUSED(Periph);}
\DoxyCodeLine{03518\ \textcolor{preprocessor}{\#if\ defined(RCC\_D3CCIPR\_LPUART1SEL)}}
\DoxyCodeLine{03519\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>D3CCIPR,\ RCC\_D3CCIPR\_LPUART1SEL));}
\DoxyCodeLine{03520\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03521\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>SRDCCIPR,\ RCC\_SRDCCIPR\_LPUART1SEL));}
\DoxyCodeLine{03522\ \textcolor{preprocessor}{\#endif\ \ }\textcolor{comment}{/*\ RCC\_D3CCIPR\_LPUART1SEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03523\ \}}
\DoxyCodeLine{03524\ }
\DoxyCodeLine{03542\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetI2CClockSource(uint32\_t\ Periph)}
\DoxyCodeLine{03543\ \{}
\DoxyCodeLine{03544\ \ \ \textcolor{keywordflow}{return}\ LL\_RCC\_GetClockSource(Periph);}
\DoxyCodeLine{03545\ \}}
\DoxyCodeLine{03546\ }
\DoxyCodeLine{03577\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetLPTIMClockSource(uint32\_t\ Periph)}
\DoxyCodeLine{03578\ \{}
\DoxyCodeLine{03579\ \ \ \textcolor{keywordflow}{return}\ LL\_RCC\_GetClockSource(Periph);}
\DoxyCodeLine{03580\ \}}
\DoxyCodeLine{03581\ }
\DoxyCodeLine{03631\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetSAIClockSource(uint32\_t\ Periph)}
\DoxyCodeLine{03632\ \{}
\DoxyCodeLine{03633\ \ \ \textcolor{keywordflow}{return}\ LL\_RCC\_GetClockSource(Periph);}
\DoxyCodeLine{03634\ \}}
\DoxyCodeLine{03635\ }
\DoxyCodeLine{03645\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetSDMMCClockSource(uint32\_t\ Periph)}
\DoxyCodeLine{03646\ \{}
\DoxyCodeLine{03647\ \ \ UNUSED(Periph);}
\DoxyCodeLine{03648\ \textcolor{preprocessor}{\#if\ defined(RCC\_D1CCIPR\_SDMMCSEL)}}
\DoxyCodeLine{03649\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>D1CCIPR,\ RCC\_D1CCIPR\_SDMMCSEL));}
\DoxyCodeLine{03650\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03651\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>CDCCIPR,\ RCC\_CDCCIPR\_SDMMCSEL));}
\DoxyCodeLine{03652\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D1CCIPR\_SDMMCSEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03653\ \}}
\DoxyCodeLine{03654\ }
\DoxyCodeLine{03666\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetRNGClockSource(uint32\_t\ Periph)}
\DoxyCodeLine{03667\ \{}
\DoxyCodeLine{03668\ \ \ UNUSED(Periph);}
\DoxyCodeLine{03669\ \textcolor{preprocessor}{\#if\ defined(RCC\_D2CCIP2R\_RNGSEL)}}
\DoxyCodeLine{03670\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>D2CCIP2R,\ RCC\_D2CCIP2R\_RNGSEL));}
\DoxyCodeLine{03671\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03672\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>CDCCIP2R,\ RCC\_CDCCIP2R\_RNGSEL));}
\DoxyCodeLine{03673\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D2CCIP2R\_RNGSEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03674\ \}}
\DoxyCodeLine{03675\ }
\DoxyCodeLine{03687\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetUSBClockSource(uint32\_t\ Periph)}
\DoxyCodeLine{03688\ \{}
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\DoxyCodeLine{03690\ \textcolor{preprocessor}{\#if\ defined(RCC\_D2CCIP2R\_USBSEL)}}
\DoxyCodeLine{03691\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>D2CCIP2R,\ RCC\_D2CCIP2R\_USBSEL));}
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\DoxyCodeLine{03694\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D2CCIP2R\_USBSEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03695\ \}}
\DoxyCodeLine{03696\ }
\DoxyCodeLine{03707\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetCECClockSource(uint32\_t\ Periph)}
\DoxyCodeLine{03708\ \{}
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\DoxyCodeLine{03710\ \textcolor{preprocessor}{\#if\ defined(RCC\_D2CCIP2R\_CECSEL)}}
\DoxyCodeLine{03711\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>D2CCIP2R,\ RCC\_D2CCIP2R\_CECSEL));}
\DoxyCodeLine{03712\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03713\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>CDCCIP2R,\ RCC\_CDCCIP2R\_CECSEL));}
\DoxyCodeLine{03714\ \textcolor{preprocessor}{\#endif\ \ }\textcolor{comment}{/*\ RCC\_D2CCIP2R\_CECSEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03715\ \}}
\DoxyCodeLine{03716\ }
\DoxyCodeLine{03717\ \textcolor{preprocessor}{\#if\ defined(DSI)}\textcolor{preprocessor}{}}
\DoxyCodeLine{03727\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetDSIClockSource(uint32\_t\ Periph)}
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\DoxyCodeLine{03730\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>D1CCIPR,\ RCC\_D1CCIPR\_DSISEL));}
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\DoxyCodeLine{03732\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ DSI\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03733\ }
\DoxyCodeLine{03743\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetDFSDMClockSource(uint32\_t\ Periph)}
\DoxyCodeLine{03744\ \{}
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\DoxyCodeLine{03746\ \textcolor{preprocessor}{\#if\ defined(RCC\_D2CCIP1R\_DFSDM1SEL)}}
\DoxyCodeLine{03747\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>D2CCIP1R,\ RCC\_D2CCIP1R\_DFSDM1SEL));}
\DoxyCodeLine{03748\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03749\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>CDCCIP1R,\ RCC\_CDCCIP1R\_DFSDM1SEL));}
\DoxyCodeLine{03750\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D2CCIP1R\_DFSDM1SEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03751\ \}}
\DoxyCodeLine{03752\ }
\DoxyCodeLine{03753\ \textcolor{preprocessor}{\#if\ defined(DFSDM2\_BASE)}\textcolor{preprocessor}{}}
\DoxyCodeLine{03763\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetDFSDM2ClockSource(uint32\_t\ Periph)}
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\DoxyCodeLine{03766\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>SRDCCIPR,\ RCC\_SRDCCIPR\_DFSDM2SEL));}
\DoxyCodeLine{03767\ \}}
\DoxyCodeLine{03768\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ DFSDM2\_BASE\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03769\ }
\DoxyCodeLine{03781\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetFMCClockSource(uint32\_t\ Periph)}
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\DoxyCodeLine{03783\ \ \ UNUSED(Periph);}
\DoxyCodeLine{03784\ \textcolor{preprocessor}{\#if\ defined(RCC\_D1CCIPR\_FMCSEL)}}
\DoxyCodeLine{03785\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>D1CCIPR,\ RCC\_D1CCIPR\_FMCSEL));}
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\DoxyCodeLine{03787\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>CDCCIPR,\ RCC\_CDCCIPR\_FMCSEL));}
\DoxyCodeLine{03788\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D1CCIPR\_FMCSEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03789\ \}}
\DoxyCodeLine{03790\ }
\DoxyCodeLine{03791\ \textcolor{preprocessor}{\#if\ defined(QUADSPI)}\textcolor{preprocessor}{}}
\DoxyCodeLine{03803\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetQSPIClockSource(uint32\_t\ Periph)}
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\DoxyCodeLine{03805\ \ \ UNUSED(Periph);}
\DoxyCodeLine{03806\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>D1CCIPR,\ RCC\_D1CCIPR\_QSPISEL));}
\DoxyCodeLine{03807\ \}}
\DoxyCodeLine{03808\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ QUADSPI\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03809\ }
\DoxyCodeLine{03810\ \textcolor{preprocessor}{\#if\ defined(OCTOSPI1)\ ||\ defined(OCTOSPI2)}\textcolor{preprocessor}{}}
\DoxyCodeLine{03822\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetOSPIClockSource(uint32\_t\ Periph)}
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\DoxyCodeLine{03824\ \ \ UNUSED(Periph);}
\DoxyCodeLine{03825\ \textcolor{preprocessor}{\#if\ defined(RCC\_D1CCIPR\_OCTOSPISEL)}}
\DoxyCodeLine{03826\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>D1CCIPR,\ RCC\_D1CCIPR\_OCTOSPISEL));}
\DoxyCodeLine{03827\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03828\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>CDCCIPR,\ RCC\_CDCCIPR\_OCTOSPISEL));}
\DoxyCodeLine{03829\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D1CCIPR\_OCTOSPISEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03830\ \}}
\DoxyCodeLine{03831\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ defined(OCTOSPI1)\ ||\ defined(OCTOSPI2)\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03832\ }
\DoxyCodeLine{03843\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetCLKPClockSource(uint32\_t\ Periph)}
\DoxyCodeLine{03844\ \{}
\DoxyCodeLine{03845\ \ \ UNUSED(Periph);}
\DoxyCodeLine{03846\ \textcolor{preprocessor}{\#if\ defined(RCC\_D1CCIPR\_CKPERSEL)}}
\DoxyCodeLine{03847\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>D1CCIPR,\ RCC\_D1CCIPR\_CKPERSEL));}
\DoxyCodeLine{03848\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03849\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>CDCCIPR,\ RCC\_CDCCIPR\_CKPERSEL));}
\DoxyCodeLine{03850\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D1CCIPR\_CKPERSEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03851\ \}}
\DoxyCodeLine{03852\ }
\DoxyCodeLine{03884\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetSPIClockSource(uint32\_t\ Periph)}
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\DoxyCodeLine{03886\ \ \ \textcolor{keywordflow}{return}\ LL\_RCC\_GetClockSource(Periph);}
\DoxyCodeLine{03887\ \}}
\DoxyCodeLine{03888\ }
\DoxyCodeLine{03900\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetSPDIFClockSource(uint32\_t\ Periph)}
\DoxyCodeLine{03901\ \{}
\DoxyCodeLine{03902\ \ \ UNUSED(Periph);}
\DoxyCodeLine{03903\ \textcolor{preprocessor}{\#if\ defined(RCC\_D2CCIP1R\_SPDIFSEL)}}
\DoxyCodeLine{03904\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>D2CCIP1R,\ RCC\_D2CCIP1R\_SPDIFSEL));}
\DoxyCodeLine{03905\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03906\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>CDCCIP1R,\ RCC\_CDCCIP1R\_SPDIFSEL));}
\DoxyCodeLine{03907\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D2CCIP1R\_SPDIFSEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03908\ \}}
\DoxyCodeLine{03909\ }
\DoxyCodeLine{03920\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetFDCANClockSource(uint32\_t\ Periph)}
\DoxyCodeLine{03921\ \{}
\DoxyCodeLine{03922\ \ \ UNUSED(Periph);}
\DoxyCodeLine{03923\ \textcolor{preprocessor}{\#if\ defined(RCC\_D2CCIP1R\_FDCANSEL)}}
\DoxyCodeLine{03924\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>D2CCIP1R,\ RCC\_D2CCIP1R\_FDCANSEL));}
\DoxyCodeLine{03925\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03926\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>CDCCIP1R,\ RCC\_CDCCIP1R\_FDCANSEL));}
\DoxyCodeLine{03927\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D2CCIP1R\_FDCANSEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03928\ \}}
\DoxyCodeLine{03929\ }
\DoxyCodeLine{03939\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetSWPClockSource(uint32\_t\ Periph)}
\DoxyCodeLine{03940\ \{}
\DoxyCodeLine{03941\ \ \ UNUSED(Periph);}
\DoxyCodeLine{03942\ \textcolor{preprocessor}{\#if\ defined(RCC\_D2CCIP1R\_SWPSEL)}}
\DoxyCodeLine{03943\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>D2CCIP1R,\ RCC\_D2CCIP1R\_SWPSEL));}
\DoxyCodeLine{03944\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03945\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>CDCCIP1R,\ RCC\_CDCCIP1R\_SWPSEL));}
\DoxyCodeLine{03946\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D2CCIP1R\_SWPSEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03947\ \}}
\DoxyCodeLine{03948\ }
\DoxyCodeLine{03959\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetADCClockSource(uint32\_t\ Periph)}
\DoxyCodeLine{03960\ \{}
\DoxyCodeLine{03961\ \ \ UNUSED(Periph);}
\DoxyCodeLine{03962\ \textcolor{preprocessor}{\#if\ defined\ (RCC\_D3CCIPR\_ADCSEL)}}
\DoxyCodeLine{03963\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>D3CCIPR,\ RCC\_D3CCIPR\_ADCSEL));}
\DoxyCodeLine{03964\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03965\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>SRDCCIPR,\ RCC\_SRDCCIPR\_ADCSEL));}
\DoxyCodeLine{03966\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D3CCIPR\_ADCSEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03967\ \}}
\DoxyCodeLine{03968\ }
\DoxyCodeLine{03972\ }
\DoxyCodeLine{03976\ }
\DoxyCodeLine{03990\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetRTCClockSource(uint32\_t\ Source)}
\DoxyCodeLine{03991\ \{}
\DoxyCodeLine{03992\ \ \ MODIFY\_REG(RCC-\/>BDCR,\ RCC\_BDCR\_RTCSEL,\ Source);}
\DoxyCodeLine{03993\ \}}
\DoxyCodeLine{03994\ }
\DoxyCodeLine{04004\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetRTCClockSource(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04005\ \{}
\DoxyCodeLine{04006\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>BDCR,\ RCC\_BDCR\_RTCSEL));}
\DoxyCodeLine{04007\ \}}
\DoxyCodeLine{04008\ }
\DoxyCodeLine{04014\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_EnableRTC(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{04017\ \}}
\DoxyCodeLine{04018\ }
\DoxyCodeLine{04024\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_DisableRTC(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04025\ \{}
\DoxyCodeLine{04026\ \ \ CLEAR\_BIT(RCC-\/>BDCR,\ RCC\_BDCR\_RTCEN);}
\DoxyCodeLine{04027\ \}}
\DoxyCodeLine{04028\ }
\DoxyCodeLine{04034\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_IsEnabledRTC(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{04036\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(RCC-\/>BDCR,\ RCC\_BDCR\_RTCEN)\ ==\ (RCC\_BDCR\_RTCEN))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04037\ \}}
\DoxyCodeLine{04038\ }
\DoxyCodeLine{04044\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_ForceBackupDomainReset(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{04047\ \}}
\DoxyCodeLine{04048\ }
\DoxyCodeLine{04054\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_ReleaseBackupDomainReset(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04055\ \{}
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\DoxyCodeLine{04061\ \}}
\DoxyCodeLine{04062\ }
\DoxyCodeLine{04132\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetRTC\_HSEPrescaler(uint32\_t\ Prescaler)}
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\DoxyCodeLine{04134\ \ \ MODIFY\_REG(RCC-\/>CFGR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad7c067c52ecd135252c691aad32c0b83}{RCC\_CFGR\_RTCPRE}},\ Prescaler);}
\DoxyCodeLine{04135\ \}}
\DoxyCodeLine{04136\ }
\DoxyCodeLine{04205\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetRTC\_HSEPrescaler(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{04207\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>CFGR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad7c067c52ecd135252c691aad32c0b83}{RCC\_CFGR\_RTCPRE}}));}
\DoxyCodeLine{04208\ \}}
\DoxyCodeLine{04209\ }
\DoxyCodeLine{04213\ }
\DoxyCodeLine{04217\ }
\DoxyCodeLine{04226\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetTIMPrescaler(uint32\_t\ Prescaler)}
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\DoxyCodeLine{04229\ \}}
\DoxyCodeLine{04230\ }
\DoxyCodeLine{04238\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_GetTIMPrescaler(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{04240\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>CFGR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6d6448d5ee420f8cc87b22b1201f5be2}{RCC\_CFGR\_TIMPRE}}));}
\DoxyCodeLine{04241\ \}}
\DoxyCodeLine{04242\ }
\DoxyCodeLine{04246\ }
\DoxyCodeLine{04247\ \textcolor{preprocessor}{\#if\ defined(HRTIM1)}\textcolor{preprocessor}{}}
\DoxyCodeLine{04251\ }
\DoxyCodeLine{04260\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_SetHRTIMClockSource(uint32\_t\ Prescaler)}
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\DoxyCodeLine{04262\ \ \ MODIFY\_REG(RCC-\/>CFGR,\ RCC\_CFGR\_HRTIMSEL,\ Prescaler);}
\DoxyCodeLine{04263\ \}}
\DoxyCodeLine{04264\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ HRTIM1\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{04265\ }
\DoxyCodeLine{04266\ \textcolor{preprocessor}{\#if\ defined(HRTIM1)}\textcolor{preprocessor}{}}
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\DoxyCodeLine{04276\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>CFGR,\ RCC\_CFGR\_HRTIMSEL));}
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\DoxyCodeLine{04281\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ HRTIM1\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{04282\ }
\DoxyCodeLine{04286\ }
\DoxyCodeLine{04298\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL\_SetSource(uint32\_t\ PLLSource)}
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\DoxyCodeLine{04300\ \ \ MODIFY\_REG(RCC-\/>PLLCKSELR,\ RCC\_PLLCKSELR\_PLLSRC,\ PLLSource);}
\DoxyCodeLine{04301\ \}}
\DoxyCodeLine{04302\ }
\DoxyCodeLine{04312\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL\_GetSource(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{04314\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>PLLCKSELR,\ RCC\_PLLCKSELR\_PLLSRC));}
\DoxyCodeLine{04315\ \}}
\DoxyCodeLine{04316\ }
\DoxyCodeLine{04322\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL1\_Enable(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{04325\ \}}
\DoxyCodeLine{04326\ }
\DoxyCodeLine{04333\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL1\_Disable(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{04336\ \}}
\DoxyCodeLine{04337\ }
\DoxyCodeLine{04343\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL1\_IsReady(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04344\ \{}
\DoxyCodeLine{04345\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(RCC-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga36cbfbda9151a0d8953f3460e07a95db}{RCC\_CR\_PLL1RDY}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga36cbfbda9151a0d8953f3460e07a95db}{RCC\_CR\_PLL1RDY}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04346\ \}}
\DoxyCodeLine{04347\ }
\DoxyCodeLine{04354\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL1P\_Enable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04355\ \{}
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\DoxyCodeLine{04357\ \}}
\DoxyCodeLine{04358\ }
\DoxyCodeLine{04365\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL1Q\_Enable(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{04368\ \}}
\DoxyCodeLine{04369\ }
\DoxyCodeLine{04376\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL1R\_Enable(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{04379\ \}}
\DoxyCodeLine{04380\ }
\DoxyCodeLine{04386\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL1FRACN\_Enable(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{04389\ \}}
\DoxyCodeLine{04390\ }
\DoxyCodeLine{04396\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL1P\_IsEnabled(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04397\ \{}
\DoxyCodeLine{04398\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVP1EN)\ ==\ RCC\_PLLCFGR\_DIVP1EN)\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04399\ \}}
\DoxyCodeLine{04400\ }
\DoxyCodeLine{04406\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL1Q\_IsEnabled(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{04408\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVQ1EN)\ ==\ RCC\_PLLCFGR\_DIVQ1EN)\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04409\ \}}
\DoxyCodeLine{04410\ }
\DoxyCodeLine{04416\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL1R\_IsEnabled(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04417\ \{}
\DoxyCodeLine{04418\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVR1EN)\ ==\ RCC\_PLLCFGR\_DIVR1EN)\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04419\ \}}
\DoxyCodeLine{04420\ }
\DoxyCodeLine{04426\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL1FRACN\_IsEnabled(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04427\ \{}
\DoxyCodeLine{04428\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_PLL1FRACEN)\ ==\ RCC\_PLLCFGR\_PLL1FRACEN)\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04429\ \}}
\DoxyCodeLine{04430\ }
\DoxyCodeLine{04437\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL1P\_Disable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04438\ \{}
\DoxyCodeLine{04439\ \ \ CLEAR\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVP1EN);}
\DoxyCodeLine{04440\ \}}
\DoxyCodeLine{04441\ }
\DoxyCodeLine{04448\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL1Q\_Disable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04449\ \{}
\DoxyCodeLine{04450\ \ \ CLEAR\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVQ1EN);}
\DoxyCodeLine{04451\ \}}
\DoxyCodeLine{04452\ }
\DoxyCodeLine{04459\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL1R\_Disable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04460\ \{}
\DoxyCodeLine{04461\ \ \ CLEAR\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVR1EN);}
\DoxyCodeLine{04462\ \}}
\DoxyCodeLine{04463\ }
\DoxyCodeLine{04469\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL1FRACN\_Disable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04470\ \{}
\DoxyCodeLine{04471\ \ \ CLEAR\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_PLL1FRACEN);}
\DoxyCodeLine{04472\ \}}
\DoxyCodeLine{04473\ }
\DoxyCodeLine{04483\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL1\_SetVCOOutputRange(uint32\_t\ VCORange)}
\DoxyCodeLine{04484\ \{}
\DoxyCodeLine{04485\ \ \ MODIFY\_REG(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_PLL1VCOSEL,\ VCORange\ <<\ RCC\_PLLCFGR\_PLL1VCOSEL\_Pos);}
\DoxyCodeLine{04486\ \}}
\DoxyCodeLine{04487\ }
\DoxyCodeLine{04499\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL1\_SetVCOInputRange(uint32\_t\ InputRange)}
\DoxyCodeLine{04500\ \{}
\DoxyCodeLine{04501\ \ \ MODIFY\_REG(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_PLL1RGE,\ InputRange\ <<\ RCC\_PLLCFGR\_PLL1RGE\_Pos);}
\DoxyCodeLine{04502\ \}}
\DoxyCodeLine{04503\ }
\DoxyCodeLine{04509\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL1\_GetN(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04510\ \{}
\DoxyCodeLine{04511\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)((READ\_BIT(RCC-\/>PLL1DIVR,\ RCC\_PLL1DIVR\_N1)\ >>\ \ RCC\_PLL1DIVR\_N1\_Pos)\ +\ 1UL);}
\DoxyCodeLine{04512\ \}}
\DoxyCodeLine{04513\ }
\DoxyCodeLine{04519\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL1\_GetM(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04520\ \{}
\DoxyCodeLine{04521\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>PLLCKSELR,\ RCC\_PLLCKSELR\_DIVM1)\ >>\ \ RCC\_PLLCKSELR\_DIVM1\_Pos);}
\DoxyCodeLine{04522\ \}}
\DoxyCodeLine{04523\ }
\DoxyCodeLine{04529\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL1\_GetP(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04530\ \{}
\DoxyCodeLine{04531\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)((READ\_BIT(RCC-\/>PLL1DIVR,\ RCC\_PLL1DIVR\_P1)\ >>\ \ RCC\_PLL1DIVR\_P1\_Pos)\ +\ 1UL);}
\DoxyCodeLine{04532\ \}}
\DoxyCodeLine{04533\ }
\DoxyCodeLine{04539\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL1\_GetQ(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04540\ \{}
\DoxyCodeLine{04541\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)((READ\_BIT(RCC-\/>PLL1DIVR,\ RCC\_PLL1DIVR\_Q1)\ >>\ \ RCC\_PLL1DIVR\_Q1\_Pos)\ +\ 1UL);}
\DoxyCodeLine{04542\ \}}
\DoxyCodeLine{04543\ }
\DoxyCodeLine{04549\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL1\_GetR(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04550\ \{}
\DoxyCodeLine{04551\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)((READ\_BIT(RCC-\/>PLL1DIVR,\ RCC\_PLL1DIVR\_R1)\ >>\ \ RCC\_PLL1DIVR\_R1\_Pos)\ +\ 1UL);}
\DoxyCodeLine{04552\ \}}
\DoxyCodeLine{04553\ }
\DoxyCodeLine{04559\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL1\_GetFRACN(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04560\ \{}
\DoxyCodeLine{04561\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>PLL1FRACR,\ RCC\_PLL1FRACR\_FRACN1)\ >>\ \ RCC\_PLL1FRACR\_FRACN1\_Pos);}
\DoxyCodeLine{04562\ \}}
\DoxyCodeLine{04563\ }
\DoxyCodeLine{04570\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL1\_SetN(uint32\_t\ N)}
\DoxyCodeLine{04571\ \{}
\DoxyCodeLine{04572\ \ \ MODIFY\_REG(RCC-\/>PLL1DIVR,\ RCC\_PLL1DIVR\_N1,\ (N\ -\/\ 1UL)\ <<\ RCC\_PLL1DIVR\_N1\_Pos);}
\DoxyCodeLine{04573\ \}}
\DoxyCodeLine{04574\ }
\DoxyCodeLine{04581\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL1\_SetM(uint32\_t\ M)}
\DoxyCodeLine{04582\ \{}
\DoxyCodeLine{04583\ \ \ MODIFY\_REG(RCC-\/>PLLCKSELR,\ RCC\_PLLCKSELR\_DIVM1,\ M\ <<\ RCC\_PLLCKSELR\_DIVM1\_Pos);}
\DoxyCodeLine{04584\ \}}
\DoxyCodeLine{04585\ }
\DoxyCodeLine{04594\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL1\_SetP(uint32\_t\ P)}
\DoxyCodeLine{04595\ \{}
\DoxyCodeLine{04596\ \ \ MODIFY\_REG(RCC-\/>PLL1DIVR,\ RCC\_PLL1DIVR\_P1,\ (P\ -\/\ 1UL)\ <<\ RCC\_PLL1DIVR\_P1\_Pos);}
\DoxyCodeLine{04597\ \}}
\DoxyCodeLine{04598\ }
\DoxyCodeLine{04605\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL1\_SetQ(uint32\_t\ Q)}
\DoxyCodeLine{04606\ \{}
\DoxyCodeLine{04607\ \ \ MODIFY\_REG(RCC-\/>PLL1DIVR,\ RCC\_PLL1DIVR\_Q1,\ (Q\ -\/\ 1UL)\ <<\ RCC\_PLL1DIVR\_Q1\_Pos);}
\DoxyCodeLine{04608\ \}}
\DoxyCodeLine{04609\ }
\DoxyCodeLine{04616\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL1\_SetR(uint32\_t\ R)}
\DoxyCodeLine{04617\ \{}
\DoxyCodeLine{04618\ \ \ MODIFY\_REG(RCC-\/>PLL1DIVR,\ RCC\_PLL1DIVR\_R1,\ (R\ -\/\ 1UL)\ <<\ RCC\_PLL1DIVR\_R1\_Pos);}
\DoxyCodeLine{04619\ \}}
\DoxyCodeLine{04620\ }
\DoxyCodeLine{04626\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL1\_SetFRACN(uint32\_t\ FRACN)}
\DoxyCodeLine{04627\ \{}
\DoxyCodeLine{04628\ \ \ MODIFY\_REG(RCC-\/>PLL1FRACR,\ RCC\_PLL1FRACR\_FRACN1,\ FRACN\ <<\ RCC\_PLL1FRACR\_FRACN1\_Pos);}
\DoxyCodeLine{04629\ \}}
\DoxyCodeLine{04630\ }
\DoxyCodeLine{04636\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL2\_Enable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04637\ \{}
\DoxyCodeLine{04638\ \ \ SET\_BIT(RCC-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga250f64c1041b823f2bd5dbbb4c54a2d5}{RCC\_CR\_PLL2ON}});}
\DoxyCodeLine{04639\ \}}
\DoxyCodeLine{04640\ }
\DoxyCodeLine{04647\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL2\_Disable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04648\ \{}
\DoxyCodeLine{04649\ \ \ CLEAR\_BIT(RCC-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga250f64c1041b823f2bd5dbbb4c54a2d5}{RCC\_CR\_PLL2ON}});}
\DoxyCodeLine{04650\ \}}
\DoxyCodeLine{04651\ }
\DoxyCodeLine{04657\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL2\_IsReady(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04658\ \{}
\DoxyCodeLine{04659\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(RCC-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga24fa002379ec3fd9063457f412250327}{RCC\_CR\_PLL2RDY}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga24fa002379ec3fd9063457f412250327}{RCC\_CR\_PLL2RDY}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04660\ \}}
\DoxyCodeLine{04661\ }
\DoxyCodeLine{04668\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL2P\_Enable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04669\ \{}
\DoxyCodeLine{04670\ \ \ SET\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVP2EN);}
\DoxyCodeLine{04671\ \}}
\DoxyCodeLine{04672\ }
\DoxyCodeLine{04679\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL2Q\_Enable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04680\ \{}
\DoxyCodeLine{04681\ \ \ SET\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVQ2EN);}
\DoxyCodeLine{04682\ \}}
\DoxyCodeLine{04683\ }
\DoxyCodeLine{04690\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL2R\_Enable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04691\ \{}
\DoxyCodeLine{04692\ \ \ SET\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVR2EN);}
\DoxyCodeLine{04693\ \}}
\DoxyCodeLine{04694\ }
\DoxyCodeLine{04700\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL2FRACN\_Enable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04701\ \{}
\DoxyCodeLine{04702\ \ \ SET\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_PLL2FRACEN);}
\DoxyCodeLine{04703\ \}}
\DoxyCodeLine{04704\ }
\DoxyCodeLine{04710\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL2P\_IsEnabled(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04711\ \{}
\DoxyCodeLine{04712\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVP2EN)\ ==\ RCC\_PLLCFGR\_DIVP2EN)\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04713\ \}}
\DoxyCodeLine{04714\ }
\DoxyCodeLine{04720\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL2Q\_IsEnabled(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04721\ \{}
\DoxyCodeLine{04722\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVQ2EN)\ ==\ RCC\_PLLCFGR\_DIVQ2EN)\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04723\ \}}
\DoxyCodeLine{04724\ }
\DoxyCodeLine{04730\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL2R\_IsEnabled(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04731\ \{}
\DoxyCodeLine{04732\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVR2EN)\ ==\ RCC\_PLLCFGR\_DIVR2EN)\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04733\ \}}
\DoxyCodeLine{04734\ }
\DoxyCodeLine{04740\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL2FRACN\_IsEnabled(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04741\ \{}
\DoxyCodeLine{04742\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_PLL2FRACEN)\ ==\ RCC\_PLLCFGR\_PLL2FRACEN)\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04743\ \}}
\DoxyCodeLine{04744\ }
\DoxyCodeLine{04751\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL2P\_Disable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04752\ \{}
\DoxyCodeLine{04753\ \ \ CLEAR\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVP2EN);}
\DoxyCodeLine{04754\ \}}
\DoxyCodeLine{04755\ }
\DoxyCodeLine{04762\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL2Q\_Disable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04763\ \{}
\DoxyCodeLine{04764\ \ \ CLEAR\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVQ2EN);}
\DoxyCodeLine{04765\ \}}
\DoxyCodeLine{04766\ }
\DoxyCodeLine{04773\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL2R\_Disable(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{04775\ \ \ CLEAR\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVR2EN);}
\DoxyCodeLine{04776\ \}}
\DoxyCodeLine{04777\ }
\DoxyCodeLine{04783\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL2FRACN\_Disable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04784\ \{}
\DoxyCodeLine{04785\ \ \ CLEAR\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_PLL2FRACEN);}
\DoxyCodeLine{04786\ \}}
\DoxyCodeLine{04787\ }
\DoxyCodeLine{04797\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL2\_SetVCOOutputRange(uint32\_t\ VCORange)}
\DoxyCodeLine{04798\ \{}
\DoxyCodeLine{04799\ \ \ MODIFY\_REG(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_PLL2VCOSEL,\ VCORange\ <<\ RCC\_PLLCFGR\_PLL2VCOSEL\_Pos);}
\DoxyCodeLine{04800\ \}}
\DoxyCodeLine{04801\ }
\DoxyCodeLine{04813\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL2\_SetVCOInputRange(uint32\_t\ InputRange)}
\DoxyCodeLine{04814\ \{}
\DoxyCodeLine{04815\ \ \ MODIFY\_REG(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_PLL2RGE,\ InputRange\ <<\ RCC\_PLLCFGR\_PLL2RGE\_Pos);}
\DoxyCodeLine{04816\ \}}
\DoxyCodeLine{04817\ }
\DoxyCodeLine{04823\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL2\_GetN(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{04825\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)((READ\_BIT(RCC-\/>PLL2DIVR,\ RCC\_PLL2DIVR\_N2)\ >>\ \ RCC\_PLL2DIVR\_N2\_Pos)\ +\ 1UL);}
\DoxyCodeLine{04826\ \}}
\DoxyCodeLine{04827\ }
\DoxyCodeLine{04833\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL2\_GetM(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04834\ \{}
\DoxyCodeLine{04835\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>PLLCKSELR,\ RCC\_PLLCKSELR\_DIVM2)\ >>\ \ RCC\_PLLCKSELR\_DIVM2\_Pos);}
\DoxyCodeLine{04836\ \}}
\DoxyCodeLine{04837\ }
\DoxyCodeLine{04843\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL2\_GetP(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04844\ \{}
\DoxyCodeLine{04845\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)((READ\_BIT(RCC-\/>PLL2DIVR,\ RCC\_PLL2DIVR\_P2)\ >>\ \ RCC\_PLL2DIVR\_P2\_Pos)\ +\ 1UL);}
\DoxyCodeLine{04846\ \}}
\DoxyCodeLine{04847\ }
\DoxyCodeLine{04853\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL2\_GetQ(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04854\ \{}
\DoxyCodeLine{04855\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)((READ\_BIT(RCC-\/>PLL2DIVR,\ RCC\_PLL2DIVR\_Q2)\ >>\ \ RCC\_PLL2DIVR\_Q2\_Pos)\ +\ 1UL);}
\DoxyCodeLine{04856\ \}}
\DoxyCodeLine{04857\ }
\DoxyCodeLine{04863\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL2\_GetR(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04864\ \{}
\DoxyCodeLine{04865\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)((READ\_BIT(RCC-\/>PLL2DIVR,\ RCC\_PLL2DIVR\_R2)\ >>\ \ RCC\_PLL2DIVR\_R2\_Pos)\ +\ 1UL);}
\DoxyCodeLine{04866\ \}}
\DoxyCodeLine{04867\ }
\DoxyCodeLine{04873\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL2\_GetFRACN(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04874\ \{}
\DoxyCodeLine{04875\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>PLL2FRACR,\ RCC\_PLL2FRACR\_FRACN2)\ >>\ \ RCC\_PLL2FRACR\_FRACN2\_Pos);}
\DoxyCodeLine{04876\ \}}
\DoxyCodeLine{04877\ }
\DoxyCodeLine{04884\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL2\_SetN(uint32\_t\ N)}
\DoxyCodeLine{04885\ \{}
\DoxyCodeLine{04886\ \ \ MODIFY\_REG(RCC-\/>PLL2DIVR,\ RCC\_PLL2DIVR\_N2,\ (N\ -\/\ 1UL)\ <<\ RCC\_PLL2DIVR\_N2\_Pos);}
\DoxyCodeLine{04887\ \}}
\DoxyCodeLine{04888\ }
\DoxyCodeLine{04895\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL2\_SetM(uint32\_t\ M)}
\DoxyCodeLine{04896\ \{}
\DoxyCodeLine{04897\ \ \ MODIFY\_REG(RCC-\/>PLLCKSELR,\ RCC\_PLLCKSELR\_DIVM2,\ M\ <<\ RCC\_PLLCKSELR\_DIVM2\_Pos);}
\DoxyCodeLine{04898\ \}}
\DoxyCodeLine{04899\ }
\DoxyCodeLine{04906\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL2\_SetP(uint32\_t\ P)}
\DoxyCodeLine{04907\ \{}
\DoxyCodeLine{04908\ \ \ MODIFY\_REG(RCC-\/>PLL2DIVR,\ RCC\_PLL2DIVR\_P2,\ (P\ -\/\ 1UL)\ <<\ RCC\_PLL2DIVR\_P2\_Pos);}
\DoxyCodeLine{04909\ \}}
\DoxyCodeLine{04910\ }
\DoxyCodeLine{04917\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL2\_SetQ(uint32\_t\ Q)}
\DoxyCodeLine{04918\ \{}
\DoxyCodeLine{04919\ \ \ MODIFY\_REG(RCC-\/>PLL2DIVR,\ RCC\_PLL2DIVR\_Q2,\ (Q\ -\/\ 1UL)\ <<\ RCC\_PLL2DIVR\_Q2\_Pos);}
\DoxyCodeLine{04920\ \}}
\DoxyCodeLine{04921\ }
\DoxyCodeLine{04928\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL2\_SetR(uint32\_t\ R)}
\DoxyCodeLine{04929\ \{}
\DoxyCodeLine{04930\ \ \ MODIFY\_REG(RCC-\/>PLL2DIVR,\ RCC\_PLL2DIVR\_R2,\ (R\ -\/\ 1UL)\ <<\ RCC\_PLL2DIVR\_R2\_Pos);}
\DoxyCodeLine{04931\ \}}
\DoxyCodeLine{04932\ }
\DoxyCodeLine{04938\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL2\_SetFRACN(uint32\_t\ FRACN)}
\DoxyCodeLine{04939\ \{}
\DoxyCodeLine{04940\ \ \ MODIFY\_REG(RCC-\/>PLL2FRACR,\ RCC\_PLL2FRACR\_FRACN2,\ FRACN\ <<\ RCC\_PLL2FRACR\_FRACN2\_Pos);}
\DoxyCodeLine{04941\ \}}
\DoxyCodeLine{04942\ }
\DoxyCodeLine{04948\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL3\_Enable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04949\ \{}
\DoxyCodeLine{04950\ \ \ SET\_BIT(RCC-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga7e7f10468741ab47dc34808af0e49b2b}{RCC\_CR\_PLL3ON}});}
\DoxyCodeLine{04951\ \}}
\DoxyCodeLine{04952\ }
\DoxyCodeLine{04959\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL3\_Disable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04960\ \{}
\DoxyCodeLine{04961\ \ \ CLEAR\_BIT(RCC-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga7e7f10468741ab47dc34808af0e49b2b}{RCC\_CR\_PLL3ON}});}
\DoxyCodeLine{04962\ \}}
\DoxyCodeLine{04963\ }
\DoxyCodeLine{04969\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL3\_IsReady(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04970\ \{}
\DoxyCodeLine{04971\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(RCC-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3ea07157abac14618b2ac3f2e9bfa9b9}{RCC\_CR\_PLL3RDY}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3ea07157abac14618b2ac3f2e9bfa9b9}{RCC\_CR\_PLL3RDY}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04972\ \}}
\DoxyCodeLine{04973\ }
\DoxyCodeLine{04980\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL3P\_Enable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04981\ \{}
\DoxyCodeLine{04982\ \ \ SET\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVP3EN);}
\DoxyCodeLine{04983\ \}}
\DoxyCodeLine{04984\ }
\DoxyCodeLine{04991\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL3Q\_Enable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{04992\ \{}
\DoxyCodeLine{04993\ \ \ SET\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVQ3EN);}
\DoxyCodeLine{04994\ \}}
\DoxyCodeLine{04995\ }
\DoxyCodeLine{05002\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL3R\_Enable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{05003\ \{}
\DoxyCodeLine{05004\ \ \ SET\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVR3EN);}
\DoxyCodeLine{05005\ \}}
\DoxyCodeLine{05006\ }
\DoxyCodeLine{05012\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL3FRACN\_Enable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{05013\ \{}
\DoxyCodeLine{05014\ \ \ SET\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_PLL3FRACEN);}
\DoxyCodeLine{05015\ \}}
\DoxyCodeLine{05016\ }
\DoxyCodeLine{05022\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL3P\_IsEnabled(\textcolor{keywordtype}{void})}
\DoxyCodeLine{05023\ \{}
\DoxyCodeLine{05024\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVP3EN)\ ==\ RCC\_PLLCFGR\_DIVP3EN)\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{05025\ \}}
\DoxyCodeLine{05026\ }
\DoxyCodeLine{05032\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL3Q\_IsEnabled(\textcolor{keywordtype}{void})}
\DoxyCodeLine{05033\ \{}
\DoxyCodeLine{05034\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVQ3EN)\ ==\ RCC\_PLLCFGR\_DIVQ3EN)\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{05035\ \}}
\DoxyCodeLine{05036\ }
\DoxyCodeLine{05042\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL3R\_IsEnabled(\textcolor{keywordtype}{void})}
\DoxyCodeLine{05043\ \{}
\DoxyCodeLine{05044\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVR3EN)\ ==\ RCC\_PLLCFGR\_DIVR3EN)\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{05045\ \}}
\DoxyCodeLine{05046\ }
\DoxyCodeLine{05052\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL3FRACN\_IsEnabled(\textcolor{keywordtype}{void})}
\DoxyCodeLine{05053\ \{}
\DoxyCodeLine{05054\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_PLL3FRACEN)\ ==\ RCC\_PLLCFGR\_PLL3FRACEN)\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{05055\ \}}
\DoxyCodeLine{05056\ }
\DoxyCodeLine{05063\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL3P\_Disable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{05064\ \{}
\DoxyCodeLine{05065\ \ \ CLEAR\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVP3EN);}
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\DoxyCodeLine{05067\ }
\DoxyCodeLine{05074\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL3Q\_Disable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{05075\ \{}
\DoxyCodeLine{05076\ \ \ CLEAR\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVQ3EN);}
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\DoxyCodeLine{05078\ }
\DoxyCodeLine{05085\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL3R\_Disable(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{05087\ \ \ CLEAR\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_DIVR3EN);}
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\DoxyCodeLine{05095\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL3FRACN\_Disable(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{05097\ \ \ CLEAR\_BIT(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_PLL3FRACEN);}
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\DoxyCodeLine{05099\ }
\DoxyCodeLine{05109\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_PLL3\_SetVCOOutputRange(uint32\_t\ VCORange)}
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\DoxyCodeLine{05111\ \ \ MODIFY\_REG(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_PLL3VCOSEL,\ VCORange\ <<\ RCC\_PLLCFGR\_PLL3VCOSEL\_Pos);}
\DoxyCodeLine{05112\ \}}
\DoxyCodeLine{05113\ }
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\DoxyCodeLine{05127\ \ \ MODIFY\_REG(RCC-\/>PLLCFGR,\ RCC\_PLLCFGR\_PLL3RGE,\ InputRange\ <<\ RCC\_PLLCFGR\_PLL3RGE\_Pos);}
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\DoxyCodeLine{05129\ }
\DoxyCodeLine{05135\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL3\_GetN(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{05138\ \}}
\DoxyCodeLine{05139\ }
\DoxyCodeLine{05145\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL3\_GetM(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{05147\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(RCC-\/>PLLCKSELR,\ RCC\_PLLCKSELR\_DIVM3)\ >>\ \ RCC\_PLLCKSELR\_DIVM3\_Pos);}
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\DoxyCodeLine{05149\ }
\DoxyCodeLine{05155\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL3\_GetP(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{05158\ \}}
\DoxyCodeLine{05159\ }
\DoxyCodeLine{05165\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL3\_GetQ(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{05168\ \}}
\DoxyCodeLine{05169\ }
\DoxyCodeLine{05175\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL3\_GetR(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{05178\ \}}
\DoxyCodeLine{05179\ }
\DoxyCodeLine{05185\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_PLL3\_GetFRACN(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{05188\ \}}
\DoxyCodeLine{05189\ }
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\DoxyCodeLine{05254\ }
\DoxyCodeLine{05255\ }
\DoxyCodeLine{05259\ }
\DoxyCodeLine{05260\ }
\DoxyCodeLine{05264\ }
\DoxyCodeLine{05270\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_ClearFlag\_LSIRDY(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{06162\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_DisableIT\_HSERDY(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{06172\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_DisableIT\_CSIRDY(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{06182\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_DisableIT\_HSI48RDY(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{06186\ }
\DoxyCodeLine{06192\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_DisableIT\_PLL1RDY(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{06202\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_DisableIT\_PLL2RDY(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{06212\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_DisableIT\_PLL3RDY(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{06222\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_RCC\_DisableIT\_LSECSS(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{06232\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_IsEnableIT\_LSIRDY(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{06322\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_RCC\_IsEnableIT\_LSECSS(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{06329\ }
\DoxyCodeLine{06330\ \textcolor{preprocessor}{\#if\ defined(USE\_FULL\_LL\_DRIVER)}\textcolor{preprocessor}{}}
\DoxyCodeLine{06334\ \textcolor{keywordtype}{void}\ LL\_RCC\_DeInit(\textcolor{keywordtype}{void});}
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\DoxyCodeLine{06342\ uint32\_t\ \ \ \ LL\_RCC\_CalcPLLClockFreq(uint32\_t\ PLLInputFreq,\ uint32\_t\ M,\ uint32\_t\ N,\ uint32\_t\ FRACN,\ uint32\_t\ PQR);}
\DoxyCodeLine{06343\ }
\DoxyCodeLine{06344\ \textcolor{keywordtype}{void}\ \ \ \ \ \ \ \ LL\_RCC\_GetPLL1ClockFreq(LL\_PLL\_ClocksTypeDef\ *PLL\_Clocks);}
\DoxyCodeLine{06345\ \textcolor{keywordtype}{void}\ \ \ \ \ \ \ \ LL\_RCC\_GetPLL2ClockFreq(LL\_PLL\_ClocksTypeDef\ *PLL\_Clocks);}
\DoxyCodeLine{06346\ \textcolor{keywordtype}{void}\ \ \ \ \ \ \ \ LL\_RCC\_GetPLL3ClockFreq(LL\_PLL\_ClocksTypeDef\ *PLL\_Clocks);}
\DoxyCodeLine{06347\ \textcolor{keywordtype}{void}\ \ \ \ \ \ \ \ LL\_RCC\_GetSystemClocksFreq(LL\_RCC\_ClocksTypeDef\ *RCC\_Clocks);}
\DoxyCodeLine{06348\ }
\DoxyCodeLine{06349\ uint32\_t\ \ \ \ LL\_RCC\_GetUSARTClockFreq(uint32\_t\ USARTxSource);}
\DoxyCodeLine{06350\ uint32\_t\ \ \ \ LL\_RCC\_GetLPUARTClockFreq(uint32\_t\ LPUARTxSource);}
\DoxyCodeLine{06351\ uint32\_t\ \ \ \ LL\_RCC\_GetI2CClockFreq(uint32\_t\ I2CxSource);}
\DoxyCodeLine{06352\ uint32\_t\ \ \ \ LL\_RCC\_GetLPTIMClockFreq(uint32\_t\ LPTIMxSource);}
\DoxyCodeLine{06353\ uint32\_t\ \ \ \ LL\_RCC\_GetSAIClockFreq(uint32\_t\ SAIxSource);}
\DoxyCodeLine{06354\ uint32\_t\ \ \ \ LL\_RCC\_GetADCClockFreq(uint32\_t\ ADCxSource);}
\DoxyCodeLine{06355\ uint32\_t\ \ \ \ LL\_RCC\_GetSDMMCClockFreq(uint32\_t\ SDMMCxSource);}
\DoxyCodeLine{06356\ uint32\_t\ \ \ \ LL\_RCC\_GetRNGClockFreq(uint32\_t\ RNGxSource);}
\DoxyCodeLine{06357\ uint32\_t\ \ \ \ LL\_RCC\_GetCECClockFreq(uint32\_t\ CECxSource);}
\DoxyCodeLine{06358\ uint32\_t\ \ \ \ LL\_RCC\_GetUSBClockFreq(uint32\_t\ USBxSource);}
\DoxyCodeLine{06359\ uint32\_t\ \ \ \ LL\_RCC\_GetDFSDMClockFreq(uint32\_t\ DFSDMxSource);}
\DoxyCodeLine{06360\ \textcolor{preprocessor}{\#if\ defined(DFSDM2\_BASE)}}
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\DoxyCodeLine{06363\ \textcolor{preprocessor}{\#if\ defined(DSI)}}
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\DoxyCodeLine{06366\ uint32\_t\ \ \ \ LL\_RCC\_GetSPDIFClockFreq(uint32\_t\ SPDIFxSource);}
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\DoxyCodeLine{06369\ uint32\_t\ \ \ \ LL\_RCC\_GetFDCANClockFreq(uint32\_t\ FDCANxSource);}
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\DoxyCodeLine{06371\ \textcolor{preprocessor}{\#if\ defined(QUADSPI)}}
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\DoxyCodeLine{06374\ \textcolor{preprocessor}{\#if\ defined(OCTOSPI1)\ ||\ defined(OCTOSPI2)}}
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\DoxyCodeLine{06377\ uint32\_t\ \ \ \ LL\_RCC\_GetCLKPClockFreq(uint32\_t\ CLKPxSource);}
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\DoxyCodeLine{06379\ }
\DoxyCodeLine{06383\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ USE\_FULL\_LL\_DRIVER\ */}\textcolor{preprocessor}{}}
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\DoxyCodeLine{06393\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ defined(RCC)\ */}\textcolor{preprocessor}{}}
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\DoxyCodeLine{06403\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ STM32H7xx\_LL\_RCC\_H\ */}\textcolor{preprocessor}{}}
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